Qorivva MPC5 Series, Руководство пользователя

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Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 35
©1989-2021 Lauterbach GmbH
If the cache lines are used as program memory (only possible for e200z6, e200z650), set
SYStem.Option ICREAD to on. Program code in a locked cache line can only be modified using access
class IC.
Support for Peripheral Modules
TRACE32 supports access to the memory mapped registers of all peripheral modules. The peripheral
register description files (*.per, so-called PER-files) for the on-chip peripherals are included in TRACE32.
PER files for recent processors are usually not included in updates, but are available upon request.
For external peripherals and/or custom peripherals, it is possible to create additional PER files with custom
content. See
“Peripheral Files Programming Commands” (per_prog.pdf) for details.
Displaying Peripheral Module Registers
Open the peripheral registers view either using the command PER.view , or open the window by menu: CPU
-> Peripherals. In order to show a certain module directly, open it by menu using MPC5XXX -> On-chip
peripherals.