Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
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If one of the affected cores is in use, one of the following changes to the core configuration can be made to
get either read-only of both read/write access.
•
To gain read-only access to all memory, configure the cache mode to write-through. This is done
via the WM or DCWM field of the L1CSR register.
•
To gain read-only access to certain memory spaces, configure or create a TLB entry for this
address range and set the W (write-through) bit.
•
To gain read/write access to all memory, the data/unified cache has to be disabled. This is done
via the L1CSR register (cache enable bit).
•
To gain read/write access to certain memory spaces, configure or create a TLB entry for this
address range and set the I (caching inhibited) bit.
Please note that these changes will impact the processor performance. Global configuration settings (like
done via L1CSR) have more impact than settings for small address ranges. Therefore it is recommended to
control the access via TLB settings and keep the page sizes for read and/or write accesses as small as
possible. For example, keep the stack memory range caching enabled, as the stack does usually not need to
be accessed via run-time memory access.
Viewing Cache Contents
The cache contents can be viewed using the
command.
The meaning of the data fields in the
window is explained in the table below. Please note
that an uninitialized cache will contain random data, therefore the data fields of the
window
will show random values as well.
Cache
Command
L1 instruction cache
L1 unified cache
CACHE.DUMP
IC
L1 data cache
CACHE.DUMP
DC
Data field
Meaning
address
Physical address of the cache line. The address is composed of
cache tag and set index.
set, way
Set and way index of the cache
v, d
Status bits of the cache line v(alid), d(irty)
#
MESI state
