Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
100
©1989-2021 Lauterbach GmbH
Enables the use of
for logical addresses to support
multiple
address spaces.
For an explanation of the TRACE32 concept of
(
, and
Examples
:
SYStem.Option NexusMemoryCoherency
Coherent NEXUS mem-access
MPC5676R and MPC5777C only
If this option is set to ON, the debugger configures the NEXUS run-time memory access to assert the signal
p_d_gbl for each access. This signal will cause the Cache Coherency Unit to perform a cache snoop for the
run-time memory access, which allows the debugger to update SRAM while maintaining cache coherency.
It is essential to set this option to ON
only
if the data cache is configured to write-through mode
(L1CSR0[DCWM]==1). If the cache is operated in copy-back mode, setting this option to ON can cause
undefined behavior.
NOTE:
SYStem.Option MMUSPACES
should not be set to
ON
if only one translation
table is used on the target.
If a debug session requires space IDs, you must observe the following
sequence of steps:
1. Activate
SYStem.Option MMUSPACES
.
2. Load the symbols with
Otherwise, the internal symbol database of TRACE32 may become
inconsistent.
;Dump logical address 0xC00208A belonging to memory space with
;space ID 0x012A:
Data.dump D:0x012A:0xC00208A
;Dump logical address 0xC00208A belonging to memory space with
;space ID 0x0203:
Data.dump D:0x0203:0xC00208A
Format:
SYStem.Option NexusMemoryCoherency
[
ON
|
OFF
]
