Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
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©1989-2021 Lauterbach GmbH
If ON, the debugger will maintain cache coherency by reading or writing directly to the cache arrays and
memory. This method guarantees that the cache tags and status bits (valid, dirty) of remain unaffected by
the memory accesses of the debugger. The debugger will also maintain cache coherency if the memory
access is done through the NEXUS block (access class “E:”, or
) is used
while the core is halted. This is the recommended setting.
If OFF, the debugger will maintain cache coherency by allowing the data/unified cache to be updated while
reading or writing memory through debug commands. Cache coherency is
not
maintained if memory is
accessed through the NEXUS block (access class “E:”, or
).
Setting DCFREEZE to OFF is reserved for a specific use case which requires an optimal data throughput
while maintaining cache coherency (while core is halted). Do not to set DCFREEZE to OFF unless advised
by Lauterbach.
SYStem.Option DCREAD
Read from data cache
Default: ON.
If enabled,
windows for access class D: (data) and variable windows display the memory values
from the d-cache, if valid. If data is not available in cache, physical memory will be read.
SYStem.Option DISableResetEscalation
Control reset escalation disabling
Default: ON.
A processor that implements the
reset escalation feature
disable itself after a certain number of resets. Once
a processor is fully escalated, a power cycle is required to regain debug access to the cores. The debugger
disables the reset escalation by default, to facilitate the debug and development process. In order to test the
behavior of the
reset escalation
in the application, set this option to OFF.
Please note that debugger-generated resets (e.g.
) also contribute to the number of resets that
trigger the
reset escalation
.
Format:
SYStem.Option DCREAD
[
ON
|
OFF
]
Format:
SYStem.Option DISableResetEscalation
[
ON
|
OFF
]
