Qorivva MPC5 Series, Руководство пользователя

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Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 31
©1989-2021 Lauterbach GmbH
The access class TLB gives access to the TLB entries of the e200 core. The TLB contents are provided in
the way they are represented in the MAS registers. The most significant byte is used to address the TLB
table:
The TLB access class is supplementary and allows reading TLBs as well as bit field modification of TLB
entries. For general MMU/MPU setup, it is recommended to use the command
MMU.Set .
The access class DBG, which covers a wide variety of accesses, has a special encoding. The encoding as
listed below is only valid for the MPC5XXX debugger.
NOTE : The registers mapped through the DBG access class are automatically configured by the debugger.
Manual changes are likely to disturb debugger/trace functionality and in most cases will be overwritten by the
debugger. Use the NEXUS commands to configure tracing instead of directly writing to the NEXUS
registers.
TLB access mask Description
TLB:0x8100iiiM
legacy access:
TLB:0x0000iiiM
Access to TLB1 table (MMU).
iii
: TLB index
M
: Byte offset to TLB content as represented in MAS registers
(0..3=MAS1, 4..7=MAS2, 8..11=MAS3, 12..15=unused)
TLB:0x8200iiiM
Access to TLB2 table (MPU).
iii
: TLB index
M
: Byte offset to TLB content as represented in MAS registers
(0..3=MAS0, 4..7=MAS1, 8..11=MAS2, 12..15=MAS3)
DBG access mask Description
DBG:0x01ttN0RR
Access to NEXUS registers of non-core NEXUS clients, e.g. NPC,
NAR, NXDM, NXFR, NXSS, NXMC, SPU and GTMDI
tt
: TAP access command (ACCESS_AUX_...)
N
: NEXUS_ENABLE command (usually zero)
RR
: NEXUS register ID
DBG:0x03ttN0RR
Same as above, but for NEXUS clients on the Buddy Device
DBG:0x02tt0CRR
Access to eTPU NEXUS registers
tt
: TAP access command (ACCESS_AUX_...)
C
: eTPU client selection
RR
: eTPU register ID
DBG:0x04tttttt
Access to DWPU tag RAM (32-bit wise)
tttttt
: Tag RAM address
(one tag RAM accesss increment = 256-byte PD memory block)
DBG:0x00000004
...
DBG:0x0000007E
e200 core NEXUS register access (address = register index * 2)
DBG:0x400 (CDACNTL)
DBG:0x401 (CDADATA)
e200 core cache debug register access