PT CPC5565, Руководство пользователя, Страница: 29 / 118

CPC5565 Functional Blocks
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The CPC5565 PTMC site provides an industry-standard interface for a high performance, dual
channel, gigabit Ethernet PMC mezzanine card. High performance is achieved by means of a
64-bit wide, 66 MHz interface that is capable of PCI or PCI-X signaling. Dual channel Ethernet
links (MDI) are routed on PTMC interface connectors J11-J14 per PICMG 2.15 configurations 5
and 6. The Ethernet links can be routed to CPC5565 rear-panel gigabit Ethernet connector J3
for connection to the CompactPCI backplane per PICMG 2.16.
Note: PCI-X is supported only when operating in Drone Mode.
The CPC5565 is backward compatible with all standard 32-bit and 64-bit PMC cards. However,
these cards do not respect the PTENB# signal. We advise caution when installing a standard
PMC card with P4 (rear I/O) signaling. Please check the pinout carefully: Connector J14 on the
CPC5565 has pins 1 - 24 set to support two 1 Gigabit Ethernet channels. Make sure this
definition does not interfere with the operation of the PMC card installed.
PMC modules interfacing to the CPC5565 must advertise their PTID (PCI Telecom Identifier)
as “configuration 7” before they are enabled (PTENB# asserted). PMC modules supporting
configurations 1, 2, 3, 4, 5, 6 will not have their PMC interface enabled by PTENB#.
The mezzanine interface is at J11-J14 on the CPC5565. See Chapter 5, “Connectors,” on
page 79 for more information.
Drone Mode
The CPC5565 can be set to operate in Drone mode when installed in a non-system slot in a
CompactPCI chassis. In Drone mode it cannot drive the system clock or the CompactPCI bus.
The CPC5565 can optionally be reset by the System Master when in a peripheral slot. See the
topic
“SW3-3 Force Drone Mode” on page 39 for more information.
Real-Time Clock, CMOS RAM and Battery
The real-time clock performs timekeeping functions and includes 256 bytes of battery-backed
CMOS RAM in two banks that are reserved for BIOS use. Timekeeping features include a time-
of-day clock and a multi-century calendar with alarm features and century rollover. The time,
date, and CMOS values can be specified or returned to their defaults by using the BIOS setup
program. See the topic
“BIOS Configuration Overview” on page 40 , for more information.
Note: The recommended method of accessing the date in systems with PT Single Board
Computers is indirectly from the real time clock via the BIOS. The BIOS on PT Single Board
Computers contains a century checking and maintenance feature. This feature checks the two
least significant digits of the year stored in the real time clock during each BIOS request (INT
1Ah) to read the date and, if less than 80 (1980 is the first year supported by the PC), updates
the century byte to 20. This feature enables operating systems and applications using the BIOS
date/time services to reliably manipulate the year as a four-digit value.
Two rechargeable button-cell batteries located on the CPC5565 power the real-time clock and
CMOS memory when the CPC5565 is not powered externally. The battery is intended for AC
power fails only and has an estimated life of 60 days (with batteries fully charged). It recharges
whenever standby power is present.
The CPC5565's real-time clock resides in the Intel 3100 chipset. The topic “I/O Controller” on
page 116 , provides a link to more information for this device.