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CPC5565 Functional Blocks
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Processor
The CPC5565 incorporates the Intel Core 2 Duo T7500 processor. The Intel Core 2 Duo T7500
processor is a 2.2 GHz, 35 W (TDP), high performance, low power, 64-bit processor that is
compatible with 32-bit applications, enabling a single architecture across 32- and 64-bit
environments.
The Intel Core 2 Duo implements dual-core technology that puts two mobile-optimized
execution cores in a single processor that is designed to increase performance with significant
power savings. Each core can complete up to four full instructions simultaneously using an
efficient 14-stage pipeline. The two cores share 4 MB of L2 cache, offering more efficient data
sharing, providing enhanced performance, responsiveness and power savings. Each core
utilizes enhanced Intel Speedstep technology on each core independently to coordinate power-
management state transitions and help save power. The 800 MHz front-side bus provides a
high-speed interconnect with the Intel 3100 chipset.
The topic “Processor” on page 117 , contains a link to additional information for this device.
Chipset
The CPC5565 incorporates the Intel 3100 integrated chipset. The Intel 3100 chipset integrates
the traditional north/south bridge functions as well as some SuperI/O and peripheral IC features
into a single IC. The Intel 3100 features:
• Processor/Host bus support:
– 64-bit, 800 MHz front-side bus interface
– Up to 36-bit host interface addressing support
– Dynamic bus inversion to minimize power consumption on the data interface
– In-Order Queue (IOQ) depth of 12, with debug support for the one-deep non-pipelined mode
– Two outstanding DEFER cycles supported
– AGTL+ driver technology with parallel termination
• Memory Interface
– Support for two dual rank, registered SO-RDIMMs with ECC
– Support for 15-bit address bus, 72-bit data bus (64-bit data plus 8-bit ECC)
– Support for base DDR2 clock rate of 200 MHz: data interface double-pumped to 400 MT/s, data
bandwidth of 3.2 GB/s
– Support for 512 Mb, 1 Gb, and 2 Gb DRAM densities
– Support for SO-RDDR2 DIMMs using x8 DRAM technology
– Aggressive page-close policy with one-deep, look-ahead to minimize occurrence of page-miss
accesses in favor of page-empty
– Support for standard SEC-DED (72, 64) ECC
– Support for automatic read retry on uncorrectable errors
– Hardware ECC auto-initialization of all populated DRAM devices under software control. Includes
pre-selected hardware pattern based memory test on programmable regions.