Phytec phyCORE-LPC2292/94, Руководство по оборудованию

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phyCORE-LPC2292/94
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PHYTEC Messtechnik GmbH 2006 L-658e_5
The Ethernet controller provides a READY output that can be
connected to the P018 input of the controller using Jumper J503. It is
also possible to combine various signal sources externally if multiple
components need to use the processor's P018 input for READY
indication.
Refer to section 3.12 for more details on applicable jumper
settings and configuration options.
The physical memory area for the Ethernet chip is defined in the
following table. An offset of 0x300 has to be added to the address of
/CS2 if Jumper J502 is closed at position 1+2 for accessing the
LAN91C111.
Ethernet Start Address
/CS2 + OFFSET 0x8200 0000 + 0x0000 0300 = 0x8200 0300
Table 40: Memory Area Ethernet Controller
9.1 MAC Address
The MAC (Media Access Control) address is a unique identification
code of computer hardware operating within a LAN (Local Area
Network). When connecting the hardware to the Internet the assigned
IP number is mapped to the MAC address via a conversion table.
The MAC addresses are administered in a central location in order to
ensure the uniqueness of these numbers. PHYTEC has purchased a
pool of such MAC addresses and each one of our Ethernet-based
Single Board Computers gets one of these addresses. The MAC
address of your phyCORE-LPC2292/94 is printed on a barcode sticker
attached to the module. The MAC address is provided as a
12-digit hexadecimal value. In addition, the MAC address is also
programmed into the Ethernet controller EEPROM (U500) at the time
of delivery. This allows immediate start-up of the module and its
Ethernet hardware. Following a hardware-reset the MAC address is
automatically loaded from the EEPROM into the Ethernet controller
(
refer to section 9.2 ).