Phytec phyCORE-LPC2292/94, Руководство по оборудованию

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phyCORE-LPC2292/94
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PHYTEC Messtechnik GmbH 2006 L-658e_5
Please refer to the corresponding controller data sheet and
application notes from Philips for more details on bus timing
configuration.
The following section contains two examples of the controller’s
configuration registers. These examples match the needs of most
standard applications for the phyCORE-LPC2292/94.
Example a)
Module Configuration:
•
Flash access time = 90 ns
•
SRAM access time = 10 ns (without PLD)
BCFG0 Register Configuration Value: 0x02000 28A3
IDCY : 3 -> 4 idle cycle
WST1 : 5 -> 8 CCLK cycles
RBLE : 0 -> 0 non byte partitioned device
WST2 : 5 -> 8 CCLK cycles
BUSERR : 0 -> not relevant
WPERR : 0 -> no write protection error
WP : 0 -> bank not write protected
BM : 0 -> no burst ROM bank
MW : 2 -> 32-bit wide bus
AT : 0 -> always write 0 to this field
BCFG1 Register Configuration Value:
0x02000 0403
IDCY : 3 -> 4 idle cycle
WST1 : 0 -> 3 CCLK cycles
RBLE : 1 -> byte partitioned device
WST2 : 0 -> only for read access
BUSERR : 0 -> not relevant
WPERR : 0 -> no write protection error
WP : 0 -> bank not write protected
BM : 0 -> no burst rom bank
MW : 2 -> 32-bit wide bus
AT : 0 -> always write 0 to this field