LTDVE8CH-20 – INSTRUCTION MANUAL
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INPUT_SEL3
: setting of input multiplexer 3
INPUT_SEL4
: setting of input multiplexer 4
INPUT_SEL5
: setting of input multiplexer 5
INPUT_SEL6
: setting of input multiplexer 6
INPUT_SEL7
: setting of input multiplexer 7
INPUT_SEL8
: setting of input multiplexer 8
INPUT_SEL9
: setting of input multiplexer 9
INPUT_SEL10
: setting of input multiplexer 10
INPUT_SEL11
: setting of input multiplexer 11
INPUT_SEL12
: setting of input multiplexer 12
INPUT_SEL13
: setting of input multiplexer 13
INPUT_SEL14
: setting of input multiplexer 14
INPUT_SEL15
: setting of input multiplexer 15
Allowed values are listed below. Avoid operation with non-listed values.
When 0x000 the input multiplexer is disabled (default value)
When 0x001 the filtered TR1 input is selected
When 0x002 the filtered TR2 input is selected
When 0x004 the filtered TR3 input is selected
When 0x008 the filtered TR4 input is selected
When 0x010 the filtered TR5 input is selected
When 0x020 the filtered TR6 input is selected
When 0x040 the filtered TR7 input is selected
When 0x080 the filtered TR8 input is selected
When 0x100 the free running oscillator is selected
Bit fields [15:9] of these registers are unused. When writing these bits, they must be set to zero.
14.2.9. Registers GEN_DLY_BASE[0:15]
Each bit field [1:0] of these sixteen registers holds the time base selector for the generation of the
pulse delay in the relevant pulse generator.
GEN_DLY_BASE0
: time base selector for generation of pulse delay in generator 1
GEN_DLY_BASE1
: time base selector for generation of pulse delay in generator 2
GEN_DLY_BASE2
: time base selector for generation of pulse delay in generator 3
GEN_DLY_BASE3
: time base selector for generation of pulse delay in generator 4
GEN_DLY_BASE4
: time base selector for generation of pulse delay in generator 5
GEN_DLY_BASE5
: time base selector for generation of pulse delay in generator 6