NXP Semiconductors UDA1352TS, Техническое описание

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2002 Nov 22 14
NXP Semiconductors Preliminary specification
48 kHz IEC 60958 audio DAC UDA1352TS
9.4 Data write mode
The data write mode is explained in the signal diagram of
Fig.5. For writing data to a device, 4 bytes must be sent
(see Table 6):
1. One byte starting with ‘01’ for signalling the write
action to the device, followed by the device address
(‘011000’ for the UDA1352TS default)
2. One byte starting with a ‘0’ for signalling the write
action, followed by 7 bits indicating the destination
register address in binary format with A6 being the
MSB and A0 being the LSB
3. One data byte (from the two data bytes) with D15
being the MSB
4. One data byte (from the two data bytes) with D0 being
the LSB.
It should be noted that each time a new destination register
address needs to be written, the device address must be
sent again.
9.5 Data read mode
To read data from the device, a prepare read must first be
done and then data read. The data read mode is explained
in the signal diagram of Fig.6.
For reading data from a device, the following 6 bytes are
involved (see Table 7):
1. One byte with the device address, including ‘01’ for
signalling the write action to the device
2. One byte is sent with the register address from which
data needs to be read; this byte starts with a ‘1’, which
indicates that there will be a read action from the
register, followed by seven bits for the source register
address in binary format, with A6 being the MSB
and A0 being the LSB
3. One byte with the device address preceded by ‘11’ is
sent to the device; the ‘11’ indicates that the device
must write data to the microcontroller
4. One byte, sent by the device to the bus, with the
(requested) register address and a flag bit indicating
whether the requested register was valid (bit is logic 0)
or invalid (bit is logic 1)
5. One byte (from the two bytes), sent by the device to
the bus, with the data information in binary format,
with D15 being the MSB
6. One byte (from the two bytes), sent by the device to
the bus, with the data information in binary format,
with D0 being the LSB.
Table 6 L3-bus write data
Table 7 L3-bus read data
BYTE
L3-BUS
MODE
ACTION
FIRST IN TIME LAST IN TIME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
1 address device address 0 1 DA0 DA1 1 0 0 0
2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0
3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8
4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0
BYTE
L3-BUS
MODE
ACTION
FIRST IN TIME LAST IN TIME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
1 address device address 0 1 DA0 DA1 1 0 0 0
2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0
3 address device address 1 1 DA0 DA1 1 0 0 0
4 data transfer register address 0 or 1 A6 A5 A4 A3 A2 A1 A0
5 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8
6 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0