2002 Nov 22
11
NXP Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
8.5.2
L3-
BUS
OR
I
2
C-
BUS
MODE
The L3-bus or I
2
C-bus mode allows maximum flexibility in controlling the UDA1352TS (see Table 4).
It should be noted that in the L3-bus or I
2
C-bus mode, several base-line functions are still controlled by pins on the device
and that, on start-up in the L3-bus or I
2
C-bus mode, the output is explicitly muted by bit MT via the L3-bus or I
2
C-bus
interface.
Table 4
Pin description in the L3-bus or I
2
C-bus mode
PIN
NAME
VALUE
FUNCTION
Mode selection pins
26
SELSTATIC
0
select L3-bus mode or I
2
C-bus mode; must be connected to V
SSD
4
SELIIC
0
select L3-bus mode; must be connected to V
SSD
1
select I
2
C-bus mode; must be connected to V
DDD
Input pins
5
RESET
0
normal operation
1
reset
8
L3DATA
−
must be connected to the L3-bus
−
must be connected to the SDA line of the I
2
C-bus
9
L3CLOCK
−
must be connected to the L3-bus
−
must be connected to the SCL line of the I
2
C-bus
10
L3MODE
−
must be connected to the L3-bus
11
MUTE
0
no mute
1
mute active
Status pins
1
PCMDET
0
non-PCM data or burst preamble detected
1
PCM data detected
16
LOCK
0
clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected
1
clock regeneration and IEC 60958 decoder locked and PCM data detected
Test pins
2
TEST1
−
must be left open-circuit
18
TEST2
0
must be connected to V
SSD
