2002 Nov 22
20
NXP Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
11 SPDIF SIGNAL FORMAT
11.1
SPDIF channel encoding
The digital signal is coded using Bi-phase Mark Code
(BMC), which is a kind of phase-modulation. In this
scheme, a logic 1 in the data corresponds to two
zero-crossings in the coded signal, and a logic 0 to one
zero-crossing. An example of the encoding is given in
Fig.10.
11.2
SPDIF hierarchical layers for audio data
From an abstract point of view an SPDIF signal can be
represented as in Fig.11. A 2-channel PCM signal can be
transmitted as various sequential blocks. Each block in
turn consists of 192 frames. Each frame contains two
sub-frames, one for each channel.
Each sub-frame is preceded by a preamble. There are
three types of preambles being B, M and W. Preambles
can be spotted easily in an SPDIF stream because these
sequences can never occur in the channel parts of a valid
SPDIF stream. Table 13 indicates the values of the
preambles.
A sub-frame in turn contains a single audio sample which
may be up to 24 bits wide, a validity bit which indicates
whether the sample is valid, a single bit of user data, and
a single bit of channel status. Finally, there is a parity bit for
this particular sub-frame (see Fig.12).
The data bits from 4 to 31 in each sub-frame will be
modulated using a BMC scheme. The sync preamble
actually contains a violation of the BMC scheme and
consequently can be detected easily.
Table 13
Preambles
11.3
SPDIF hierarchical layers for digital data
The difference with the audio format is that the data
contained in the SPDIF signal is not audio but is digital
data.
When transmitting digital data via SPDIF using the
IEC 60958 protocol, the allocation of the bits inside the
data word is done as shown in Table 14.
Table 14
Bit allocation for digital data
As shown in Table 14 and Fig.13, the non-PCM encoded
data bitstreams are transferred within the basic 16 bits
data area of the IEC 60958 sub-frames [time-slots
12 (LSB) to 27 (MSB)].
handbook, halfpage
data
clock
BMC
MGU606
Fig.10 Bi-phase mark encoding.
PRECEDING
STATE
CHANNEL CODING
0
1
B
1110 1000
0001 0111
M
1110 0010
0001 1101
W
1110 0100
0001 1011
FIELD
IEC 60958 TIME
SLOT BITS
DESCRIPTION
0 to 3
preamble
according to IEC 60958
4 to 7
auxiliary bits
not used; all logic 0
8 to 11
unused data bits
not used; all logic 0
12
16 bits data
sections of the digital
bitstream
13
user data
according to IEC 60958
14 to 27
16 bits data
sections of the digital
bitstream
28
validity bit
according to IEC 60958
29
user data
according to IEC 60958
30
channel status bit
according to IEC 60958
31
parity bit
according to IEC 60958
