2002 Nov 22
15
NXP Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
9.6
Initialization string
For proper and reliable operation, the UDA1352TS must be initialized in the L3-bus mode. This is required to have the
PLL start-up after powering up of the device under all conditions. The initialization string is given in Table 8.
Table 8
L3-bus initialization string and set defaults after power-up
BYTE
L3-BUS
MODE
ACTION
FIRST IN TIME
LAST IN TIME
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
1
address
init string
device address
0
1
DA0
DA1
1
0
0
0
2
data transfer
register address
0
1
0
0
0
0
0
0
3
data transfer
data byte 1
0
0
0
0
0
0
0
0
4
data transfer
data byte 2
0
0
0
0
0
0
0
1
5
address
set
defaults
device address
0
1
DA0
DA1
1
0
0
0
6
data transfer
register address
0
1
1
1
1
1
1
1
7
data transfer
data byte 1
0
0
0
0
0
0
0
0
8
data transfer
data byte 2
0
0
0
0
0
0
0
0
10 I
2
C-BUS DESCRIPTION
10.1
Characteristics of the I
2
C-bus
The bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to the V
DD
via a pull-up resistor when
connected to the output stages of a microcontroller. For a
400 kHz IC the recommendation for this type of bus from
NXP Semiconductors must be followed (e.g. up to loads of
200 pF on the bus a pull-up resistor can be used, between
200 to 400 pF a current source or switched resistor must
be used). Data transfer can only be initiated when the bus
is not busy.
10.2
Bit transfer
One data bit is transferred during each clock pulse (see
Fig.7). The data on the SDA line must remain stable during
the HIGH period of the clock pulse as changes in the data
line at this time will be interpreted as control signals. The
maximum clock frequency is 400 kHz.
To be able to run on this high frequency all the inputs and
outputs connected to this bus must be designed for this
high-speed I
2
C-bus according to specification
“The
I
2
C-bus and how to use it”
, (order code 9398 393 40011).
handbook, full pagewidth
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.7 Bit transfer on the I
2
C-bus.
