20
02
N
o
v
2
2
1
8
NXP Semiconductors
Preli
m
inary specification
48 kHz IEC 60958 audio DAC
U
DA1352TS
10.10 Write cycle
The I
2
C-bus configuration for a write cycle is shown in Table 11. The write cycle is used to write the data to the internal registers. The device and register
addresses are one byte each, the setting data is always a pair of two bytes.
The format of the write cycle is as follows:
1.
The microcontroller starts with a start condition (S).
2.
The first byte (8 bits) contains the device address ‘1001 110’ and a logic 0 (write) for the R/W bit.
3.
This is followed by an acknowledge (A) from the UDA1352TS.
4.
After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1352TS must start.
5.
The UDA1352TS acknowledges this register address (A).
6.
The microcontroller sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an
acknowledge is followed from the UDA1352TS.
7.
If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the
UDA1352TS.
8.
Finally, the UDA1352TS frees the I
2
C-bus and the microcontroller can generate a stop condition (P).
Table 11
Master transmitter writes to the UDA1352TS registers in the I
2
C-bus mode.
Note
1.
Auto increment of register address.
DEVICE
ADDRESS
R/W
REGISTER
ADDRESS
DATA 1
DATA 2
DATA n
S
1001 110
0
A
ADDR
A
MS1
A
LS1
A
MS2
A
LS2
A
MSn
A
LSn
A
P
acknowledge from UDA1352TS
