UM10147_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 28 April 2008
62 of 134
NXP Semiconductors
UM10147
P89LPC952/954 User manual
10.10 More about UART Mode 0
In Mode 0, a write to SnBUF will initiate a transmission. At the end of the transmission,
TI_n(SnCON.1) is set, which must be cleared in software. Double buffering must be
disabled in this mode.
Table 57.
Serial Port 1 Status register (S1STAT - address D4h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DBMOD
_1
INTLO_1 CIDIS_1
DBISEL_
1
FE_1
BR_1
OE_1
STINT_1
Reset
x
x
x
x
x
x
0
0
Table 58.
Serial Port 1 Status register (S1STAT - address D4h) bit description
Bit Symbol
Description
0
STINT_1 Status Interrupt Enable 1. When set = 1, FE_1, BR_1, or OE_1 can cause an
interrupt. The interrupt used (vector address 008Bh) is shared with RI (CIDIS_1 =
1) or the combined TI/RI (CIDIS_1 = 0). When cleared = 0, FE_1, BR_1, OE_1
cannot cause an interrupt. (Note: FE_1, BR_1, or OE_1 is often accompanied by a
RI, which will generate an interrupt regardless of the state of STINT_1.
1
OE_1
Overrun Error 1 flag is set if a new character is received in the receiver buffer while
it is still full (before the software has read the previous character from the buffer),
i.e., when bit 8 of a new byte is received while RI_1 in S1CON is still set. Cleared
by software.
2
BR_1
Break Detect flag. A break is detected when any 11 consecutive bits are sensed
low. Cleared by software.
3
FE_1
Framing error flag is set when the receiver fails to see a valid STOP bit at the end
of the frame. Cleared by software.
4
DBISEL
_1
Double buffering transmit interrupt select. Used only if double buffering is enabled.
This bit controls the number of interrupts that can occur when double buffering is
enabled. When set, one transmit interrupt is generated after each character written
to S1BUF, and there is also one more transmit interrupt generated at the beginning
(INTLO_1 = 0) or the end (INTLO_1 = 1) of the STOP bit of the last character sent
(i.e., no more data in buffer). This last interrupt can be used to indicate that all
transmit operations are over. When cleared = 0, only one transmit interrupt is
generated per character written to S1BUF. Must be logic 0 when double buffering
is disabled. Note that except for the first character written (when buffer is empty),
the location of the transmit interrupt is determined by INTLO_1. When the first
character is written, the transmit interrupt is generated immediately after S1BUF is
written.
5
CIDIS_1 Combined Interrupt Disable 1. When set = 1, Rx and Tx interrupts are separate.
When cleared = 0, the UART 1 uses a combined Tx/Rx interrupt (like a
conventional 80C51 UART). This bit is reset to logic 0 to select combined
interrupts.
6
INTLO_
1
Transmit interrupt position 1. When cleared = 0, the Tx interrupt is issued at the
beginning of the stop bit. When set = 1, the Tx interrupt is issued at end of the stop
bit. Must be logic 0 for mode 0. Note that in the case of single buffering, if the Tx
interrupt occurs at the end of a STOP bit, a gap may exist before the next start bit.
7
DBMOD
_1
Double buffering mode 1. When set = 1 enables double buffering. Must be logic 0
for UART mode 0. In order to be compatible with existing 80C51 devices, this bit is
reset to logic 0 to disable double buffering.
