UM10147_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 28 April 2008
23 of 134
NXP Semiconductors
UM10147
P89LPC952/954 User manual
2.3 Clock output
The P89LPC952/954 supports a user-selectable clock output function on the XTAL2 /
CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a
different clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on X1) and if the Real-time Clock is not using the crystal oscillator as
its clock source. This allows external devices to synchronize to the P89LPC952/954. This
output is enabled by the ENCLK bit in the TRIM register
The frequency of this clock output is
1
⁄
2
that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on
reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when
setting or clearing the ENCLK bit, the user should retain the contents of other bits of the
TRIM register. This can be done by reading the contents of the TRIM register (into the
ACC for example), modifying bit 6, and writing this result back into the TRIM register.
Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6
of the TRIM register.
2.4 On-chip RC oscillator option
The P89LPC952 has a 6-bit TRIM register that can be used to tune the frequency of the
RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed
value to adjust the oscillator frequency to 7.373 MHz
±
1 % at room temperature. (Note:
the initial value is better than 1 %; please refer to the
P89LPC952/954 data sheet
for
behavior over temperature). End user applications can write to the TRIM register to adjust
the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease
the oscillator frequency. When the clock doubler option is enabled (UCFG1.3 = 1), the
output frequency is doubled. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7)
can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing
highest performance access. This bit can then be set in software if CCLK is running at
8 MHz or slower.
The requirements in
Section 2.2.4 “High speed oscillator option”
for configuring P1.5 as
an external reset input and using an external reset circuit when the clock frequency is
greater than 12 MHz do
not
apply when using the internal RC oscillator’s clock doubler
option.
Table 5.
On-chip RC oscillator trim register (TRIM - address 96h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
RCCLK
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
Reset
0
0
Bits 5:0 loaded with factory stored value during reset.
