UM10147_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 28 April 2008
30 of 134
NXP Semiconductors
UM10147
P89LPC952/954 User manual
3.2.3 Conversion start modes
3.2.3.1
Timer triggered start
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started,
additional Timer 0 triggers are ignored until the conversion has completed. The Timer
triggered start mode is available in all A/D operating modes.This mode is selected by the
TMMx bit and the ADCS01 and ADCS00 bits (see
).
3.2.3.2
Start immediately
Programming this mode immediately starts a conversion.This start mode is available in all
A/D operating modes.This mode is selected by setting the ADCS01 and ADCS00 bits in
the ADCON0 register (See
and
).
3.2.3.3
Edge triggered
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has
started, additional edge triggers are ignored until the conversion has completed. The edge
triggered start mode is available in all A/D operating modes.This mode is selected by
setting the ADCS01 and ADCS00 bits in the ADCON0 register (See
and
).
3.2.4 Stopping and restarting conversions
An A/D conversion or set of conversions can be stopped by clearing the ADCS01 and
ADCS00 bits in ADCON0 (and also theTMM0 bit in ADCON0 if the conversion was started
in Timer triggered mode). Prior to resuming conversions, the user will need to reset the
input multiplexer to the first user specified channel. This can be accomplished by writing
the ADINS register with the desired channels.
3.2.5 Boundary limits interrupt
The A/D converter has both a high and low boundary limit register. The user may select
whether an interrupt is generated when the conversion result is within (or equal to) the
high and low boundary limits or when the conversion result is outside the boundary limits.
An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria.
The boundary limit may be disabled by clearing the boundary limit interrupt enable.
An early detection mechanism exists when the interrupt criteria has been selected to be
outside the boundary limits. In this case, after the four MSBs have been converted, these
four bits are compared with the four MSBs of the boundary high and low registers. If the
four MSBs of the conversion meet the interrupt criteria (i.e.- outside the boundary limits)
an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt
criteria, the boundary limits will again be compared after all 8 MSBs have been converted.
The boundary status register (BNDSTA0) flags the channels which caused a boundary
interrupt.
3.2.6 Clock divider
The A/D converter requires that its internal clock source be in the range of 320 kHz to
9 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to
8 is provided for this purpose (See
