NXP Semiconductors MPC5566, Справочное руководство

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-39
The DSPI ignores attempts to push data to a full TX FIFO; that is, the state of the TX FIFO is unchanged.
No error condition is indicated.
20.4.3.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO counter
is decremented by one. At the end of a transfer, the TCF bit in the DSPI
x _SR is set to indicate the
completion of a transfer. The TX FIFO is flushed by writing a 1 to the CLR_TXF bit in DSPI x _MCR.
If an external SPI bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is
empty, the transmit FIFO underflow flag (TFUF) in the slave’s DSPI
x _SR is set.
See Section 20.4.9.4, “Transmit FIFO Underflow Interrupt Request (TFUF) ,”for details.
20.4.3.5 Using the RX FIFO Buffering Mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds four received
SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the received data
in the shift register is transferred into the RX FIFO. SPI data is removed (popped) from the RX FIFO by
reading the DSPI
x _POPR register. RX FIFO entries can only be removed from the RX FIFO by reading
the DSPI x _POPR or by flushing the RX FIFO.
See Section 20.3.2.7, “DSPI POP RX FIFO Register (DSPIx_POPR) ” for more information on the
DSPI x _POPR.
The RX FIFO counter field (RXCTR) in the DSPI status register (DSPI x _SR) indicates the number of
valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is
copied from the shift register to the RX FIFO.
The POPNXTPTR field in the DSPI x _SR points to the RX FIFO entry that is returned when the
DSPI x _POPR is read. The POPNXTPTR contains the positive, 32-bit word offset from DSPI x _RXFR0.
For example, POPNXTPTR equal to two means that the DSPI x _RXFR2 contains the received SPI data
that is returned when DSPI x _POPR is read. The POPNXTPTR field is incremented every time the
DSPI x _POPR is read. POPNXTPTR rolls over every four frames on the MCU.
20.4.3.5.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred
to the RX FIFO the RX FIFO counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPI x _SR is set
indicating an overflow condition. Depending on the state of the ROOE bit in the DSPI x _MCR, the data
from the transfer that generated the overflow is ignored or put in the shift register. If the ROOE bit is set,
the incoming data is put in the shift register. If the ROOE bit is cleared, the incoming data is ignored.