UM10429
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© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
43 of 258
NXP Semiconductors
UM10429
Chapter 5: LPC1102 Power profiles
5.4.1.4.3
Exact solution cannot be found (PLL)
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_EQU;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock and a system clock of exactly
25 MHz. The application was ready to infinitely wait for the PLL to lock. Since there is no
valid PLL setup within earlier mentioned restrictions,
set_pll
returns
PLL_FREQ_NOT_FOUND in
result[0]
and 12000 in
result[1]
without changing the PLL
settings.
5.4.1.4.4
System clock less than or equal to the expected value
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_LTE;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of no more than
25 MHz and no locking timeout.
set_pll
returns PLL_CMD_SUCCESS in
result[0]
and
24000 in
result[1]
. The new system clock is 24 MHz.
5.4.1.4.5
System clock greater than or equal to the expected value
command[0] = 12000;
command[1] = 25000;
command[2] = CPU_FREQ_GTE;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of at least 25 MHz
and no locking timeout.
set_pll
returns PLL_CMD_SUCCESS in
result[0]
and 36000 in
result[1]
. The new system clock is 36 MHz.
5.4.1.4.6
System clock approximately equal to the expected value
command[0] = 12000;
command[1] = 16500;
command[2] = CPU_FREQ_APPROX;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock, a system clock of approximately
16.5 MHz and no locking timeout.
set_pll
returns PLL_CMD_SUCCESS in
result[0]
and
16000 in
result[1]
. The new system clock is 16 MHz.
