22 PFC_DDD_v1.3.doc
MR
Reset In
R12
R10
3V3
1V6
RESET
VCC
A_PORESET
PORESET_M1
PORESET_FPGA
MSC8101
GPIO[PA7]
FLASH
FPGA
MSC8102
MSC8102
MSC8102
MSC8102
MSC8102
A_PORESET_M1
Figure 12. PORESET Scheme
The MSC8101 controls the generation of individually buffered HRESET signals to the MSC8102s
through the AND gating of its own HRESET signal and its HRESET GPIO control line PD31. Note
that for flexibility the MSC8102 HRESETS have been routed to the FPGA via 0ohm resistors.
The PMCC signal PTMC_RESET can be used by a prospective PFC base card host to control the
HRESET of the PFC.
The SRESET signals for the MSC8101 and MSC8102s have all been pulled high.
A_HRESET
PTMC Connector
Pn2 pin 13
MSC8101
HRESET
PD31
MSC8102
MSC8102
MSC8102
MSC8102
MSC8102
A_M_HRESET
PTMC_RESET
HRESET signals
(pulled up)
Figure 13. HRESET Scheme
5.4.2
Clock Distribution
The PFC has two clock regions
1.
MSC8101 Aggregator and MSC8102 DSI interface clocking, Figure 14
2.
MSC8102 and associated SDRAM clocking, Figure 15
In the first clock region the MSC8101 Aggregator and MSC8102 DSI interface clocks (HCK) are
generated via a single oscillator, which is distributed via an ICS9112-17 low skew buffer.
In the second clock region the MSC8102 CLKIN signals are generated from a single oscillator, which
is distributed via the ICS9112-16 low skew output buffer to the MSC8102 farm. Each MSC8102
CLKOUT signal is in turn fed back as the DLLIN signal via an additional low skew buffer. This buffer
also generates the MSC8102’s associated SDRAM clock
To accommodate debug and board set up the following clock frequencies are used on the MSC8101
and MSC8102.
Table 21. MSC8101 Clock frequencies
Clock Mode
CLKIN
Core
CPM
Bus
46
34.5 MHz
275 MHz
138 MHz
69 MHz
Table 22. MSC8102 Clock frequencies
Clock Mode
CLKIN
Core
Bus
DSI
10
41.6 MHz
250 MHz
83 MHz
69 MHz
