12 PFC_DDD_v1.3.doc
A_BADDR[31] A-1
On the flash the BYTE signal is pulled down for byte mode which enables DQ[0:7] but tri-states
DQ[8:14], with DDQ15/A-1 used as an input for the LSB address bit, A_BADDR31. The memory
controller uses the BADDR[27-31] signals to interface to the memories when operating in multi-
master mode.
5.2.3
MSC8101 60x to DSI Interface
The 60x-DSI interface is the main means of communications between the Aggregator and the DSP
Farm. The DSI interface is configurable, and can be set to either 32 or 64bit wide, as well as
synchronous or asynchronous modes
•
Asynchronous Mode: SRAM-like interface enabling the host single accesses (with no external
clock). Data is transferred using the MSC8101 Memory Controller’s UPM.
•
Synchronous Mode: SSRAM-like interface enabling host single or burst accesses of 256 bits
(8 accesses of 32 bits or 4 accesses of 64 bits) with its external clock decoupled from the
MSC8102 internal bus clock. Data transferred in this mode is passed onto the external 60x
bus to be handled by the FPGA
The DSI gives external hosts direct access to the MSC8102 internal memory space, including on-chip
memories and the registers of the on-chip modules. The DSI write buffer stores the address and the
data of the accesses until they are performed. The external host can therefore perform multiple writes
without waiting for those accesses to complete. Latencies that are typical during accesses to on-chip
memories are greatly reduced by the DSI read prefetch mechanism. The host addresses each of the
MSC8102 devices using a single chip-select with the most significant bits on the address bus
identifying the addressed MSC8102 device. The 4-bit MSC8102 DSI address is hardwired via
CHIP_ID[0:3], Table 13
Table 13. MSC8102 DSI Addresses
MSC8102
CHIP_ID[0:3]
1 0000
2 0001
3 0010
4 0011
5 0100
The host can also write the same data to multiple MSC8102 devices simultaneously by asserting a
dedicated broadcast chip select.
5.2.3.1
MSC8101 60x to DSI Interface: Synchronous mode
In synchronous mode an FPGA is required to interface between the MSC8101 60x bus and the
MSC8102 DSI port. The connectivity is detailed in Figure 6.
