32 PFC_DDD_v1.3.doc
6
Firmware Implementation
This section describes the firmware implementation on the PFC board, which includes detailed
memory maps and register settings and details on how the board is bootstrapped.
6.1
MSC8101 Host Memory Controller Settings
The PFC MSC8101 host DSP uses 6 of the available chip selects as memory resources. Four of these
are used for peripherals (Flash, SDRAM, DSI, DSI Broadcast) and 2 are used for internal resources
(SRAM and Local Peripherals), which creates a memory map, illustrated in Table 30. Note that when
in synchronous DSI mode chips selects are not required for DSI and DSI broadcast as transfers are
handled by the external 60x bus (FPGA). The DSI mapping of the MSC8102 when viewed through the
DSI port is also detailed. Note that only the local bus can see the core side memory area (i.e. local
SRAM which is mapped from 0x00000000 to 0x0007FFFF) and peripherals like HDI16 etc.
The Base and option register settings, which define the memory map, are detailed in Table 30 with
Chip Select 10 & 11 automatically set up as part of the ROM boot sequence. In addition to these
registers the Bus Configuration Register should be set for multi-master mode BCR[EBM]=1 when
using synchronous DSI.
Table 30. MSC8101 Memory Controller Resources
Chip
Select
Device
Start
Address
End Address
Size
BR[x]
OR[x]
CS0 Flash
(Boot) 0xFE00_0000
0xFE3F_FFFF 4MB 0xFE000801
0xFFC00EF4
CS2 SDRAM
0x2000_0000 0x20FF_FFFF 8MB 0x20001841
0xFF803290
CS3 DSI
Broadcast 0x22A0_0000
0x22BF_FFFF 2MB 0x22A01881
0xFFE00104
DSP 5
0x2280_0000
0x229F_FFFF
2MB
DSP 4
0x2260_0000
0x227F_FFFF
2MB
DSP 3
0x2240_0000
0x225F_FFFF
2MB
DSP 2
0x2220_0000
0x223F_FFFF
2MB
CS4 DSI
DSP 1
0x2200_0000
0x221F_FFFF
2MB
0x22001881 0xFF000100
CS10 Internal
SRAM 0x0200_0000 0x0207_FFFF 512KB 0x020000c1 0xFFF80000
CS11 Local
Bus
Peripherals
0x01F0_0000 0x01F0_7FFF 32KB 0x01F00021 0xFFFF0000
