11 PFC_DDD_v1.3.doc
Step 3. Issue Precharge All command (PALL) to all banks of the device. Program PSDMR[OP] bits to
[101] and then perform an access to the SDRAM bank.
Step 4. Issue 8 or more CBR Refresh (REF) commands. Program PSDMR[OP] bits to [001] and then
perform 8 accesses to the SDRAM bank.
Step 5. Issue Mode Register Set (MRS) command to initialise the mode register. Program
PSDMR[OP] bits to [011] and then performing an access to the SDRAM bank at an address offset to
0x08Csee figure below.
0
0
0
0
1
0
0
0
1
1
BT
CAS Latency
WB
Op Mode
0
RSVD
Burst Length
0
0
0
0
1
0
0
0
1
1
0
0
0
SDRAM
Address
Lines
MSC8101
Address
Lines
NC
SDRAM Only sees this part of the Bus
BL = Burst Length 8 for 32 Bit bus.
BT = 0 Sequential Bursts
CAS Latency = 2
OP MODE = Standard Operation
WB = 0 Programmed Burst Length
A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
A10/
AP
Figure 4. MSC8101 SDRAM Mode Register Settings
5.2.1.2
SDRAM Refresh
The SDRAM requires 4096 refresh cycles per 64ms or one refresh cycle per 15.625
µ
s. The MSC8101
can be programmed to carry out the refresh cycle periodically using the SDRAM Refresh Timer
(PSRT). By setting the memory refresh timer prescaler register, MPTPR[PTP] to divide by 32, and the
PSRT to 0x30 a timer period of 15.625
µ
s is realized for a 100MHz system clock . For a 69MHz
System clock PSRT = 0x17.
Figure 5. Refresh Calculations
5.2.2
MSC8101 FLASH Interface
The Aggregator incorporates an AM29LV320DB-120E 4Mx8-bit FLASH for Stand-alone reset
configuration and boot. To enable bootstrapping from reset the Flash is mapped to GPCM CS0 and
utilizes the following signals
Table 12. MSC8102 DSI Addresses
MSC8102
GPCM Signal
A_CS_FLASH CS0
A_PSDRAS POE
A_PSDDQMO WE
A_BADDR[27:30] A[3:0]
30
0
1
625
.
15
32
100
x
PSRT
us
x
MHz
PSRT
od
xTimerPeri
F
PSRT
MPTC
=
−
=
=
20
0
1
625
.
15
32
69
x
PSRT
us
x
MHz
PSRT
od
xTimerPeri
F
PSRT
MPTC
=
−
=
=
