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NXP Semiconductors Digital DNA MSC8102, Руководство пользователя и подробное описание конструкции оборудования

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17 PFC_DDD_v1.3.doc 

Table 17.  HDI6 Configuration 

60x signal 

HDI16 Signal 

Description 

Dh57 

HDSP=0 

Single data strobe mode 

Dh58 

HDDS=0 

Negative data strobe polarity 

Dh59 H8BIT=0 

16-bit 

mode 

enabled 

Dh60 

HCS2=1 

Not used, pulled high 

Note that when using the host port the DSI interface must be configured for 32-bits 

5.3

 

MSC8102 DSP Processing Array 

The DSP farm contains 5 MSC8102 DSPs connected to the MSC8101 via a shared DSI 60x bus 
interface. Each DSP has access to 16MB of SDRAM. The DSPs interface to the PSTN world through 
the PTMC connector via their TDM links. In addition MSC8102 DSP1 (U19) has an SMC UART 
connection to an onboard connector. 

5.3.1

 

DSP Array SDRAM Configuration 

Each DSP incorporates 128M-bit x32-bit wide x4 bank Micron MT48LC4M32B2 SDRAM surface 
mounted onto the board providing 16 MBytes of general-purpose system RAM. The MSC8102’s Chip 
Select 2 is used to select the SDRAM devices through the SDRAM controller, which is capable of 
interfacing to JEDEC compatible SDRAM, the settings of which are now described. 

•

 

SDRAM size is 1M x 32 x 4 Banks = 16MBytes, which requires 24 address lines. 

•

 

Device has 8 column and 12 Row lines, 2 Bank Selects. The 32-bit port size means addresses 
30 and 31 are not used. 

For Page based interleaving the 60x bus is arranged as follows: 

A[8:19] 

A[20:21] 

A[22:29] 

A[30:31] 

Row (x12) 

Bank Select 

Column (x8) 

LSB 

 

This gives the following MSC8101 Registers settings: 

•

 

PSDMR[PBI]  = 1, Page Based Interleaving 

•

 

ORx[BPD]  = 01,  4 Banks per device 

•

 

ORx[ROWST]  = 1000,  Row Starts at A8 

•

 

ORx[NUMR]= 011, SDRAM has 12 Row lines 

 

From the SDRAM perspective during an ACTIVATE command it’s address port will look like: 

A9:A19 

A16:A17 

A18:A29 

A30:A31 

--- Internal 

Bank 

Select 

(A[20:21]) 

Row(A[8:19]) LSB 

 

While a Read/Write will look like: 

A9:A19 

A16:A17 

A[18:21] 

A[22:29] 

A30:A31 

--- Internal 

Bank 

Select 

(A[20:21]) 

Don’t 

care 

Column 

(A[22:29]) 

LSB 

 

This gives the following register settings: 

•

 

PSDMR[SDAM] = 010, A[9:19] multiplexed to A[19:29] 

•

 

PSMDR[BSMA] = 011, A[16-17] are used as Bank Selects Signals 

•

 

PSMDR[SDA10] = 001, A9 maps to A10/AP pin 

The full PSDMR settings are described in table 

Содержание Digital DNA MSC8102

Страница 1: ...e Motorola Ltd Jays Close Viables Industrial Estate Basingstoke Hants RG22 4PD registration No 912182 England Author Colin McEwan Mark Knox Email colin mcewan motorola com mark knox motorola com Phone...

Страница 2: ...story Revision By Date Description of Change 1 0 CM 24 1 3 First Issue 1 1 CM 7 3 3 Updated toreflectPilot Production Boards 1 2 CM 27 3 3 MSC8102 SDRAM increased to16MB 1 3 CM 21 4 3 Pilot Production...

Страница 3: ...5 2 5 MSC8101 FCC Interface 15 5 2 6 RMII Interface 16 5 2 7 MSC8101 I2C Controller 16 5 2 8 MSC8101 RS232 Interface 16 5 2 9 MSC8101 Host Interface HDI16 16 5 3 MSC8102 DSP PROCESSING ARRAY 17 5 3 1...

Страница 4: ...TABLE 3 MSC8102 BOOT THROUGH DSI 5 TABLE 4 FULL CHAIN JTAG OF 21 5 TABLE 5 MSC8101 DEFAULT RESET CONFIGURATION WORD 5 TABLE 6 MSC8101 HDI16 BOOT 6 TABLE 7 JTAG OPTIONS 6 TABLE 8 MSC8101 MEMORY CONTROL...

Страница 5: ...iv PFC_DDD_v1 3 doc TABLE 36 CT BUS 39 TABLE 37 ETHERNET INTERFACE 40 TABLE 38 MISCELLANEOUS SIGNALS 40...

Страница 6: ...this document Table 1 Reference Documents Reference Document Number Description Revision Date 1 IEEE P1386 1 Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC Draft 2 4 January 1...

Страница 7: ...e Media Gateway is configured as PT3MC a subset of the PTMC specification which supports UTOPIA RMII and CT bus interfaces on Jn3 4 An optional fifth connector Jn5 has been added to support the two MI...

Страница 8: ...e CT Bus via PTMC interface 64 bit 32 bit DSI Slave port interfacing to the MSC8101 PPC via FPGA for data distribution DSI Asynchronous mode of operation DSI Synchronous mode of operation 16MByte of S...

Страница 9: ...g modes MSC8101 Boot from Flash o Operating frequency 275 MHz Core 138 MHz CPM 69MHz system bus MSC8102 Boot through DSI o Operating frequency 250MHz core 83MHz system bus o 32 bit asynchronous DSI JT...

Страница 10: ...ISYNC 0 DSI operates in asynchronous mode SW2 6 ON SWTE 0 Software WDT disabled SW2 7 ON RSTCONF 0 MSC8102 Boot over DSI Keeps MSC8102s in reset until RCW received SW3 6 SW3 7 OFF ON BM2 MSC8102 Boot...

Страница 11: ...tch SW3 5 can be used to select the required MSC8101 CPM options as detailed below Table 7 MSC8101 Ethernet Utopia Options Feature Settings Comments SW3 5 ON FCC1 UTOPIA FCC2 Ethernet MII2 SW3 5 OFF F...

Страница 12: ...ration file for 21 cores is listed in Appendix C 4 3 Programming Flash The PFC uses the same Flash AM29LV320DB as the MSC8102ADS so the option exists to use either the Metrowerks Code warrior or PFC s...

Страница 13: ...8101 aggregator for bootstrap and ongoing data exchange and control 4 MB of 8 bit wide Flash is connected to the MSC8101 60x bus for configuration boot and execution code for all 6 DSPs 8 MBytes of 32...

Страница 14: ...t used For Page based Interleaving the 60x bus is arranged as follows A 9 19 A 20 21 A 22 29 A 30 31 Row x11 Bank Select Column x8 LSB This gives the following MSC8101 Registers settings PSDMR PBI 1 P...

Страница 15: ...e conservative and can be optimized for future configurations The OR BR settings are described below Table 11 MSC8101 BR OR settings Register Setting Description BA 0x2000_0 Base Address 0x20000000 PS...

Страница 16: ...9 A30 A31 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 AP Figure 4 MSC8101 SDRAM Mode Register Settings 5 2 1 2 SDRAM Refresh The SDRAM requires 4096 refresh cycles per 64ms or one refresh cycle per 15 625 s The...

Страница 17: ...passed onto the external 60x bus to be handled by the FPGA The DSI gives external hosts direct access to the MSC8102 internal memory space including on chip memories and the registers of the on chip m...

Страница 18: ...TSIZ 0 3 Xilinix XC2S300E 7F G456C MSC8101 A_PSDQM 0 7 FPGA_CK A_TS A_TBST A_PSDVAL A_CLK_OUT Ah 0 31 A_TT 0 4 A_BADDR 27 31 A_BCTL 0 1 GRP_Ah 7 29 A_AACK A_TA A_CS_HCS A_CS_HBCS A_ALE GRP_Ds 0 63 HBR...

Страница 19: ...UT_D2 MSC8102 3 IRQ1_D3 IRQ2_D3 GPIO30_D3 INT_OUT_D3 MSC8102 4 IRQ1_D4 IRQ2_D4 GPIO30_D4 INT_OUT_D4 MSC8102 5 IRQ1_D5 IRQ2_D5 GPIO30_D5 INT_OUT_D5 A_IRQ1 MSC 8101 FPGA MSC8102 1 INT_OUT_D1 MSC8102 2 M...

Страница 20: ...x7 MII1 RxD0 Pn4 40 Pn5 46 PA18 FCC1 Utopia II Tx7 MII1 TxD0 Pn4 35 Pn5 41 PA19 FCC1 Utopia II Tx6 MII1 TxD1 Pn4 37 Pn5 43 PA20 FCC1 Utopia II Tx5 MII1 TxD2 Pn4 47 Pn5 45 PA21 FCC1 Utopia II Tx4 MII1...

Страница 21: ...on to the PTMC Type III RMII port on connector PN3 5 2 7 MSC8101 I2C Controller An I2C Management for customer specific application is incorporated on the MSC8101 via J14 Pin 57 SDA and J14 Pin 9 SCL...

Страница 22: ...oller which is capable of interfacing to JEDEC compatible SDRAM the settings of which are now described SDRAM size is 1M x 32 x 4 Banks 16MBytes which requires 24 address lines Device has 8 column and...

Страница 23: ...for an extra cycle BUFCMD 0 Normal Timing for the control lines CL 10 Cycle CAS Latency 2 PSDMR 0xC267378A MSC8102 SDRAM These SDRAM settings are conservative and can be optimized for future configura...

Страница 24: ...Programmed Burst Length A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 AP Figure 9 SDRAM Mode Register Settings 5 3 1 2 SDRAM Refresh The SDRAM requires 4096 ref...

Страница 25: ...TDM3TSYN TDM0TDAT TDM0RDAT TDM1TDAT TDM1RDAT TDM2TDAT TDM2RDAT TDM3TDAT TDM3RDAT MSC8102 TDM0TCLK TDM0TSYN TDM1TCLK TDM1TSYN TDM2TCLK TDM2TSYN TDM3TCLK TDM3TSYN TDM0TDAT TDM0RDAT TDM1TDAT TDM1RDAT TD...

Страница 26: ...UART is provided through the MSC8102 s serial communications interface SCI to give programmable debug or communications capability A Maxim MAX3232CUE provides the level conversion for the interface N...

Страница 27: ...ESET Scheme 5 4 2 Clock Distribution The PFC has two clock regions 1 MSC8101 Aggregator and MSC8102 DSI interface clocking Figure 14 2 MSC8102 and associated SDRAM clocking Figure 15 In the first cloc...

Страница 28: ...01 derived clocks FPGA_CK SDRAMCKA A_DLLIN HCK_D 1 5 are of equal length On the MSC8102s the signals D1_DLLINx SDRMCKx are of equal length MSC8101 MSC8102 1 MSC8102 3 MSC8102 2 MSC8102 4 MSC8102 5 SDR...

Страница 29: ...oltage is 1 5 4 1 VR R R Vfb Vout Vfb 1 0V R4 R5 1K and VR 2K Vout Vfb R4 R5 VR1 Figure 16 Setting Vout with Resistor Divider The FPGA requires 1V8 supply and a minimum 500mA for a few millisecs on po...

Страница 30: ...C CP14_D0 22 23 CP13_D6 GND 24 25 GND CP14_D1 26 27 CP13_D5 CP14_D2 28 29 CP13_D4 5V 30 31 CP13_D3 CP14_D3 32 33 CP13_D2 GND 34 35 GND CP14_D4 36 37 CP13_D1 5V 38 39 GND CP14_D5 40 41 CP13_D0 CP14_D6...

Страница 31: ...21 GND HDS 22 23 HD4 3 3V 24 25 HD5 HTREQ 26 27 3 3V HRREQ 28 29 HD6 GND 30 31 HD7 A_IRQ7 32 33 GND HCS 34 35 HD8 3 3V 36 37 GND NC 38 39 HD9 GND 40 41 3 3V NC 42 43 HD10 GND 44 45 HD11 NC 46 47 GND...

Страница 32: ...21 NC RMII_TXEN0 22 23 NC RMII_CRS_DV0 24 25 CT_C8_A GND 26 27 GND CT_D19 28 29 CT_D18 CT_D17 30 31 CT_D16 GND 32 33 GND NC 34 35 CT_D14 NC 36 37 CT_D12 GND 38 39 PTENB NC 40 41 NC NC 42 43 NC GND 44...

Страница 33: ...0 21 5V TXENB 22 23 GND RXADR2 24 25 TXCLK GND 26 27 GND TXADR1 28 29 TXADR0 RXADR1 30 31 TXPRTY GND 32 33 GND RXADR0 34 35 TXD7 RXPRTY 36 37 TXD6 GND 38 39 5V RXD7 40 41 GND RXD6 42 43 RXCLK GND 44 4...

Страница 34: ...xamination analysis of registers memory and on chip peripherals The EONCE module interfaces with the debugging system through on chip JTAG TAP controller pins The DSP s EONCE JTAG debug ports are conn...

Страница 35: ...re CPM Bus operating frequencies SW3 4 MSC8101 Boot Option ON Host Port disabled Boot from external memory OFF Host Port enabled Boot from HDI16 SW3 5 IO SEL for MSC8101 UTOPIA Ethernet multiplexed Se...

Страница 36: ...E ON Software WDT disabled OFF Software WDT enabled SW2 7 Reset Configuration SW2 1 SW2 7 ON ON Reset configuration write through 60x bus ON OFF Reset Configuration write through 60x bus defaults to a...

Страница 37: ...SRAM which is mapped from 0x00000000 to 0x0007FFFF and peripherals like HDI16 etc The Base and option register settings which define the memory map are detailed in Table 30 with Chip Select 10 11 auto...

Страница 38: ...60x Bus Shows DSP 1 only DSI Broadcast 0x22A0_0000 Figure 18 MSC8101 Host Memory Map 6 2 MSC8102 Memory Controller Settings Each PFC MSC8102 slave DSP uses 4 of the available chip selects as memory r...

Страница 39: ...Word for the MSC8101 is given in Table 32 Table 32 MSC8101 Hard Reset Configuration Word Bit Name Value Description 0 EARB 0 Internal Arbitration 1 EXMC 0 Internal Memory Controller 2 IRQ7 INT 1 INT_...

Страница 40: ...ORESET has been released the MSC8101 reads its own Reset Configuration Word from Flash There is then a set delay to allow the PLL and DLL to lock after this the HRESET is released At this stage the MS...

Страница 41: ...tion Jump to address 0x69000 and run Downloader code Copy Init code from Flash 0xFE010000 to SRAM 0x0 Execute Bootstrap code Write RCW to MSC8102 over DSI Download code from DSI MSC8102 ROM BOOT Initi...

Страница 42: ...layout is detailed below Figure 21 PFC Base Card Layout 7 1 UTOPIA Interface When the cards are connected the PFC MSC8101 interfaces directly with the UTOPIA PHY on the ADS with BRG8 supplying the clo...

Страница 43: ...A_TXPRTY Pn4 31 PD16 P2 A16 UTOPIA_TXENB Pn4 22 ATMTXENb P2 B1 UTOPIA_RXSOC Pn4 64 ATMRSOC P2 B5 UTOPIA_RXCLAV Pn4 18 ATMRCA P2 B6 UTOPIA_RXCLK UT_MI_CLK2 Uses CLK7 in UTOPIA mode Pn4 43 ATMRCLK OUTPU...

Страница 44: ...2 16 HA3 P2 D32 HDI16_HRW Pn2 20 HRDRW P2 A23 HDI16_HDS Pn2 22 HWRDS P2 A24 HTREQ Pn2 26 HREQTRQ P2 D21 HRREQ Pn2 28 HRRQACK P2 D24 HDI16_HCS HCS2 not used Pn2 34 HCS1 P2 A22 7 4 CT Bus Interface Ther...

Страница 45: ...38 FETHCRS P2 C6 MII2_TXEN Pn5 33 FETHTXEN P2 C3 MII2_TXER Pn5 35 FETHTXER P2 C1 MII2_COL Pn5 37 FETHCOL P2 C5 MII2_TXD0 Pn5 21 FETHTXD0 P2 C10 MII2_TXD1 Pn5 23 FETHTXD1 P2 C9 MII2_TXD2 Pn5 25 FETHTXD...

Страница 46: ...OR MOSFET N CHANNEL 30V Fairchild Semiconductor FDS6670A U5 IC RS 232 TRANSCEIVER 3 5 5V 1Mbps MAXIM MAX3232CUE U6 LOGIC GATE QUAD 2 INPUT AND LCX CMOS TSSOP 14PIN ON Semiconductor MC74LCX08DT U7 IC L...

Страница 47: ...DDD_v1 3 doc U36 EEPROM FLASH 2MX16 4MX8 TSSOP 48PIN AMD AM29LV320DB120EI U37 IC DSP 332PIN BGA MOTOROLA MSC8101 U39 IC FPGA 1 8V Spartan IIE Xilinix XC2S300E 7FG456C VR1 2K2 variable res Bourns 3214W...

Страница 48: ...JP2 2 way Low Profile PCB Screw terminal 5mm pitch IMO 20 501 2SB J1 J2 Right Angle Male Connector 128pin type D ERNI 023816 DIN41612 J3 H 100 Connector AMP 1 557100 7 J4 cPCI Connector right angle 22...

Страница 49: ...6 MSC8102 DSP4 Core 1 7 MSC8102 DSP4 Core 2 8 MSC8102 DSP4 Core 3 9 MSC8102Sync MSC8102 DSP3 Core 0 11 MSC8102 DSP3 Core 1 12 MSC8102 DSP3 Core 2 13 MSC8102 DSP3 Core 3 14 MSC8102Sync MSC8102 DSP2 Cor...

Страница 50: ...45 PFC_DDD_v1 3 doc Appendix D PFC Layout Figure 22 PFC Layout Top Figure 23 PFC Layout Bottom...

Страница 51: ...46 PFC_DDD_v1 3 doc MSC8102PFCUG D Rev 1 3...

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