10 PFC_DDD_v1.3.doc
OP = 000
Normal Operation
SDAM = 010
A[9:19] multiplexed to A[19:29]
BSMA = 100
A17-A18 are used as Bank Selects Signals
SDA10 = 001
A9 maps to A10/AP pin
RFRC = 110
8 Clock Cycles Refresh Recovery
PRETOACT = 011
Pre-charge to Activate 3 cycle interval
ACTTORW= 011
Activate to Read/Write 3 clock cycles
BL 23 = 1
Burst Length is 8
LDOTOPRE = 10
Precharge can be set 2 cycles before last data is read from SDRAM
WRC = 00
Precharge is set 4 cycles after the last data is written to SDRAM
EAMUX= 1
External Address Multiplexing, Fastest timing (set to 0 for MSC8102
SDRAM)
BUFCMD = 0
Normal Timing for the control lines
CL = 10
Cycle CAS Latency=2
PSDMR = 0xC287378A: MSC8101 SDRAM
These SDRAM settings are conservative and can be optimized for future configurations.
The OR & BR settings are described below:
Table 11. MSC8101 BR & OR settings
Register Setting
Description
BA=0x2000_0
Base Address = 0x20000000
PS=11
32-bit port size
MSEL =010
SDRAM machine
0x20001841
Register Setting
Description
SDAM = 1111 1111
1000
LSDAM = 0000 0
8MB SDRAM
BPD= 01
4 Banks Per Device
ROWST = 1001
Row Starts at A9
NUMR = 010
SDRAM has 11 Row lines
PMSEL = 0
Back to Back Page Mode (Normal Operation)
IBID =
1
Bank
Interleaving
Disabled
OR = 0xFF803290
After Power On a JEDEC standard initialization sequence is performed to configure the SDRAM. This
is carried out in Software utilizing the SDRAM controller PSDMR register:
5.2.1.1
SDRAM Initialization Command Sequence
Step 1. Apply power and start clock. Maintain No Operation (NOP) condition at the inputs.
Step 2. Maintain stable power, stable clock and NOP input conditions at the inputs.
