29 PFC_DDD_v1.3.doc
PIN
SIGN AL
SIGN AL
PIN
1
NC
1V6
2
3
NC
NC
4
5
NC
NC
6
7
NC
NC
8
9
1V6
NC
10
11
1V6
GND
12
13
NC
NC
14
15
NC
NC
16
17
NC
NC
18
19
GND
M II2_TCLK
20
21
M II2_TXD0
1V6
22
23
M II2_TXD1
M II2_ RXDV
24
25
M II2_TXD2
M II2_RXD0
26
27
M II2_TXD3
M II2_RXD1
28
29
1V6
M II2_RXD2
30
31
1V6
GND
32
33
M II2_TXEN
M II2_RXD3
34
35
M II2_TXER
M II2_RXER
36
37
M II2_ COL
M II2_CRS
38
39
GND
M II2_RCLK
40
41
M II1_TXD0
VCC_CORE
42
43
M II1_TXD1
M II1_ RXDV
44
45
M II1_TXD2
M II1_RXD0
46
47
M II1_TXD3
M II1_RXD1
48
49
1V6
M II1_RXD2
50
51
1V6
GND
52
53
M II1_TXEN
M II1_RXD3
54
55
M II1_TXER
M II1_RXER
56
57
M II1_ COL
M II1_CRS
58
59
GND
M II1_RCLK
60
61
1V6
GND
62
63
1V6
M II1_TCLK
64
Table 27. Pn5/Jn5 Connector Pin Out (Ethernet)
5.4.6
JTAG Connectivity
The MSC810x’s EONCE module allows non-intrusive interaction with the SC140 core allowing
examination/analysis of registers, memory and on-chip peripherals. The EONCE module interfaces
with the debugging system through on-chip JTAG TAP controller pins.
The DSP’s EONCE JTAG debug ports are connected in a chain configuration to allow simultaneous
debug of the complete DSP Array and Aggregator. There are a number of configurations:
•
Setting JP1 jumper to position 1-2 and switch 2_8 to ON (short) enables the debug of the full
chain.
•
Setting JP1 jumper to position 2-3 and switch 2_8 to OFF (open) enables the debug of only
the MSC8101.
•
MSC8102s can be removed/added to the chain as required by the removal/addition of various
0 ohm resistors.
An EONCE connector is provided on P3. The signals available on the connector are:
•
TMS: This signal is pulled up so that after reset 5 TCK clocks will put the TAP into the
Test Logic Reset State,
•
TSRT: The Reset signal is pulled low to force the JTAG into reset by default.
•
TCK:
The clock signal is pulled low (pulled high is also OK for this signal) to save power
in low power stop mode.
