NEC READY ES PRO, Руководство пользователя

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84 System specifications
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math coprocessor
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full backward compatibility.
The processor comes mounted in the latest 321-pin zero-insertion-
force (ZIF) socket (Socket 7). The socket allows easy processor
upgrades with next generation processors.
Secondary cache
The secondary cache compliments the processor’s internal caches.
The secondary cache uses burst pipelined synchronous static random
access memory (BSRAM) and tag RAM. Cache memory improves
read performance by holding copies of code and data that are
frequently requested from system memory by the processor.
The cache is connected directly to the processor address bus and uses
physical addresses. A bus feature known as pipeline burst enables fast
cache fills. Memory areas (pages) can be designated as cacheable or
non-cacheable by software. The cache can be enabled or disabled by
software.
The write strategy of the cache (both primary and secondary) is write-
back and write-through organization. If the write is a cache hit, an
external bus cycle is not generated and information is written to the
cache. An area of memory can be cached in the system. Non-
cacheable portions of memory are defined by software. The cache can
be cleared by software instructions
System memory
The system comes with 32 MB of 60-ns SDRAM memory installed
on the system board. Two sockets (socket 0 and socket 1) on the
system board support up to 128 MB of high-speed memory using
industry-standard gold-plated dual in-line modules (DIMMs).