NEC MuPD78F0132H, Руководство пользователя

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CHAPTER 5 CLOCK GENERATOR
User’s Manual U16899EJ2V0UD
114
(3) Main clock mode register (MCM)
This register sets the CPU clock (high-speed system clock/Ring-OSC clock).
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-4. Format of Main Clock Mode Register (MCM)
Address: FFA1H After reset: 00H R/W
Note
Symbol 7 6 5 4 3 2 <1> <0>
MCM 0 0 0 0 0 0 MCS MCM0
MCS CPU clock status
0 Operates with Ring-OSC clock
1 Operates with high-speed system clock
MCM0 Selection of clock supplied to CPU
0 Ring-OSC clock
1 High-speed system clock
Note Bit 1 is read-only.
Cautions 1. When Ring-OSC clock is selected as the clock to be supplied to the CPU, the
divided clock of the Ring-OSC oscillator output (f
X
) is supplied to the peripheral
hardware (f
X
= 240 kHz (TYP.)).
Operation of the peripheral hardware with Ring-OSC clock cannot be
guaranteed. Therefore, when Ring-OSC clock is selected as the clock supplied
to the CPU, do not use peripheral hardware. In addition, stop the peripheral
hardware before switching the clock supplied to the CPU from the high-speed
system clock to the Ring-OSC clock. Note, however, that the following
peripheral hardware can be used when the CPU operates on the Ring-OSC
clock.
•
Watchdog timer
•
Clock monitor
•
8-bit timer H1 when f
R
/2
7
is selected as count clock
•
Peripheral hardware selecting external clock as the clock source
(Except when external count clock of TM0n (n = 0, 1) is selected (TI00n valid
edge))
2. Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to high-
speed system clock operation (bit 4 (CSS) of the processor clock control
register (PCC) is changed from 1 to 0).