NEC MuPD78F0132H, Руководство пользователя

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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U16899EJ2V0UD
184
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
The following four registers are used to control 8-bit timer/event counters 50 and 51.
•
Timer clock selection register 5n (TCL5n)
•
8-bit timer mode control register 5n (TMC5n)
•
Port mode register 1 (PM1) or port mode register 3 (PM3)
•
Port register 1 (P1) or port register 3 (P3)
(1) Timer clock selection register 5n (TCL5n)
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by an 8-bit memory manipulation instruction.
RESET input clears TCL5n to 00H.
Remark n = 0, 1
Figure 7-5. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TCL50 0 0 0 0 0 TCL502 TCL501 TCL500
TCL502 TCL501 TCL500 Count clock selection
Note
0 0 0 TI50 pin falling edge
0 0 1 TI50 pin rising edge
0 1 0 f
X
(10 MHz)
0 1 1 f
X
/2 (5 MHz)
1 0 0 f
X
/2
2
(2.5 MHz)
1 0 1 f
X
/2
6
(156.25 kHz)
1 1 0 f
X
/2
8
(39.06 kHz)
1 1 1 f
X
/2
13
(1.22 kHz)
Note Be sure to set the count clock so that the following condition is satisfied.
•
V
DD
= 4.0 to 5.5 V: Count clock
≤
10 MHz
•
V
DD
= 3.3 to 4.0 V: Count clock
≤
8.38 MHz
•
V
DD
= 2.7 to 3.3 V: Count clock
≤
5 MHz
•
V
DD
= 2.5 to 2.7 V: Count clock
≤
2.5 MHz
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 8-bit timer/event counter 50 is not guaranteed.
2. When rewriting TCL50 to other data, stop the timer operation beforehand.
3. Be sure to clear bits 3 to 7 to 0.
Remarks 1. f
X
: High-speed system clock oscillation frequency
2. Figures in parentheses apply to operation at f
X
= 10 MHz.