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MCF5272 User’s Manual
Background Debug Mode (BDM)
5.5.1 CPU Halt
Although most BDM operations can occur in parallel with CPU operations, unrestricted
BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt
are listed below in order of priority:
1. A catastrophic fault-on-fault condition automatically halts the processor.
2. A hardware breakpoint can be configured to generate a pending halt condition
similar to the assertion of BKPT. This type of halt is always first made pending in
the processor. Next, the processor samples for pending halt and interrupt conditions
once per instruction. When a pending condition is asserted, the processor halts
execution at the next sample point. See Section 5.6.1, “Theory of Operation.”
3. The execution of a HALT instruction immediately suspends execution. Attempting
to execute HALT in user mode while CSR[UHE] = 0 generates a privilege violation
exception. If CSR[UHE] = 1, HALT can be executed in user mode. After HALT
executes, the processor can be restarted by serial shifting a
GO
command into the
debug module. Execution continues at the instruction after HALT.
4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt
condition is postponed until the processor core samples for halts/interrupts. The
processor samples for these conditions once during the execution of each
instruction. If there is a pending halt condition at the sample time, the processor
suspends execution and enters the halted state.
The assertion of BKPT should be considered in the following two special cases:
•
After the system reset signal is negated, the processor waits for 16 processor clock
cycles before beginning reset exception processing. If the BKPT input is asserted
within eight cycles after RSTI is negated, the processor enters the halt state,
signaling halt status (0xF) on the PST outputs. While the processor is in this state,
all resources accessible through the debug module can be referenced. This is the
only chance to force the processor into emulation mode through CSR[EMU].
After system initialization, the processor’s response to the
GO
command depends on
the set of BDM commands performed while it is halted for a breakpoint.
Specifically, if the PC register was loaded, the
GO
command causes the processor to
exit halted state and pass control to the instruction address in the PC, bypassing
normal reset exception processing. If the PC was not loaded, the
GO
command
causes the processor to exit halted state and continue reset exception processing.
•
The ColdFire architecture also handles a special case of BKPT being asserted while
the processor is stopped by execution of the STOP instruction. For this case, the
processor exits the stopped mode and enters the halted state, at which point, all BDM
commands may be exercised. When restarted, the processor continues by executing
the next sequential instruction, that is, the instruction following the STOP opcode.
CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt
conditions.
Содержание DigitalDNA ColdFire MCF5272
Страница 1: ...MCF5272UM D Rev 0 02 2001 MCF5272 ColdFire Integrated Microprocessor User s Manual ...
Страница 38: ...xxxviii MCF5272 User s Manual TABLES Table Number Title Page Number ...
Страница 58: ...1 10 MCF5272 User s Manual MCF5272 Specific Features ...
Страница 90: ...2 42 MCF5272 User s Manual Exception Processing Overview ...
Страница 96: ...3 6 MCF5272 User s Manual MAC Instruction Execution Timings ...
Страница 158: ...5 46 MCF5272 User s Manual Motorola Recommended BDM Pinout ...
Страница 184: ...7 12 MCF5272 User s Manual Interrupt Controller Registers ...
Страница 338: ...13 44 MCF5272 User s Manual Application Examples ...
Страница 414: ...18 6 MCF5272 User s Manual PWM Programming Model ...
Страница 452: ...19 38 MCF5272 User s Manual Power Supply Pins ...
Страница 482: ...20 30 MCF5272 User s Manual Reset Operation ...
Страница 492: ...21 10 MCF5272 User s Manual Non IEEE 1149 1 Operation ...
Страница 548: ...INDEX Index 12 MCF5272 User s Manual ...