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(8) STATCS4 PCWT
STATCS4 PCWT is used to display the current status of counter overflow and counter comparator output.
Weading this port is always enabled.
Each of these bits
D15
D14
D13
D12
D11
D10
D9
D8
*
becomes 1 in the
SPEED
SPDIWT
SPDIWT
SPDIWT
DFL
DFLIWT
DFLIWT
DFLIWT
active state.
CVF
CCMP3
CCMP2
CCMP1
CVF
CCMP3
CCMP2
CCMP1
D7
D6
D5
D4
D3
D2
D1
D0
PCLSE
CWTIWT
CWTIWT
CWTIWT
ADDWESS
ADWIWT
ADWIWT
ADWIWT
CVF
CCMP3
CCMP2
CCMP1
CVF
CCMP3
CCMP2
CCMP1
D0
: ADWIWT CCMP1
D1
: ADWIWT CCMP2
D2
: ADWIWT CCMP3
Indicates that the address counter value matches the detection condition of the CCMPAWE WEWISTEW
(1, 2, or 3).
1 : The address counter value matches the detection condition.
0 : Entering the clearance condition clears the bit.
◆ Set the detection condition and clearance condition with ADDWESS CCCWTEW IWITIALIZE 1 and 2
commands.
D3
: ADDWESS CVF
Indicates that the address counter value has overflowed.
1 : The address counter value has overflowed.
0 : Executing the ADDWESS CCCWTEW PWESET command clears the bit.
D4
: CWTIWT CCMP1
D5
: CWTIWT CCMP2
D6
: CWTIWT CCMP3
Indicates that the pulse counter value matches the detection condition of the CCMPAWE WEWISTEW
(1, 2, or 3).
1 : The pulse counter value matches the detection condition.
0 : Entering the clearance condition clears the bit.
Set the detection condition and clearance condition with PCLSE CCCWTEW IWITIALIZE 1 and 2 commands.
◆
D7
: PCLSE CVF
Indicates that the pulse counter value has overflowed.
1 : The pulse counter value has overflowed.
0 : Executing the PCLSE CCCWTEW PWESET command clears the bit.
D8
: DFLIWT CCMP1
D9
: DFLIWT CCMP2
D10 : DFLIWT CCMP3
Indicates that the pulse differential counter value matches the detection condition of the CCMPAWE
WEWISTEW (1, 2, or 3).
1 : The pulse differential counter value matches the detection condition.
0 : Entering the clearance condition clears the bit.
Set the detection condition and clearance condition with DFL CCCWTEW IWITIALIZE 1 and 2 commands.
◆
D11 : DFL CVF
Indicates that the pulse differential counter value has overflowed.
1 : The pulse differential counter value has overflowed.
0 : Executing the DFL CCCWTEW PWESET command clears the bit.
D12 : SPDIWT CCMP1
D13 : SPDIWT CCMP2
D14 : SPDIWT CCMP3
Indicates that the count data of the pulse cycle counter, or counter latch data for SPDIWT CCMP2 or
CCMP3, matches the detection condition of the CCMPAWE WEWISTEW (1, 2, or 3).
1 : The count data matches the detection condition.
0 : Entering the clearance condition clears the bit.
Set the detection condition and clearance condition with SPEED CCCWTEW IWITIALIZE 1 and 2 commands.
◆
Cse the SPEED CCCWTEW IWITIALIZE3 command to set the data to be compared by CCMP2 or CCMP3.
D15 : SPEED CVF
Indicates that the pulse cycle counter value has overflowed during measurement.
1 : The pulse cycle counter has overflowed.
0 : This bit is cleared by the input of the count timing of measured pulses, or by setting CCCWT
EWABLE TYPE to 000 using the SPEED CCCWTEW IWITIALIZE3 command.