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Dividing function and measurement timing of pulse cycle counter
■
The count timing cycle of a pulse that is selected by CCCWT PCLSE SEL is divided and measured.
Count timing of pulse to be measured
●
Input of rise timing
Input of fall timing
Count timing (logical
1
2
3
4
5
6
7
CW of rise and fall)
Measurement timing of CCCWT PCLSE SEL2 = 0 (measurement of one cycle of pulse)
●
Starting trigger signal
Measurement start
Measurement start
STBY
Measurement timing
with divide count 1
1
2
3
4
5
6
7
Measurement timing
with divide count 2
1
3
5
7
First measurement data 0
Measurement timing of CCCWT PCLSE SEL2 = 1 (used as a timer)
●
Starting trigger signal
Measurement start
Measurement start
Measurement timing
with divide count 1
1
2
3
4
5
6
7
Measurement timing
with divide count 2
2
4
6
Speed conversion expression for latch data
■
latch data speed (Hz)
V ＝ F／ D
： V ＝
latch data
： D ＝
＝ (１ ／ D) x 100
： F ＝ 20,000,000 (Hz)
Error (%)
The resolution of the pulse cycle counter is 50 ns.
Speed measurement has an error of ± 50 ns.
I
f a higher accuracy is required, extend the measurement cycle using the dividing function.
Data setting of pulse cycle counter
■
The measurement data of the pulse cycle counter is a count of 20 MHz clocks.
To write to the CCCWTEW DATA1,2,3 PCWT and CCCWTEW CCMMAWD PCWT, set a Compare register detection
value and overflow counter value.
