Mallinckrodt NELLCOR NPB-4000, Руководство по обслуживанию

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Section 13: Microprocessor Computer and Control –Theory of Operation
13-17
13.10.1 LCD Control
There are two chip selects assigned to the LCD display chip: one for the control
registers inside the chip, and one for the display memory space. The chip itself
has a state machine controller inside, and generates the necessary signals to store
and retrieve data from the memory when requested. It also takes care of driving
the LCD display directly, with the data from the display SRAM.
The circuit uses the 1351 in mode 5 and the 16-bit microprocessor interface
configuration. All transfers are word oriented, and byte reads and writes are not
allowed.
The processor interface consists of the following signals .
IOCS# is the control register chip select and connects directly with CS0#
from the 386EX. To program the 1351 registers, the software selects
this address and transfers the data.
MEMCS# is the display memory select signal. It is connected to CS1#
directly and display data is transferred to the display ram using this
address space.
IORD#, IOWR#, MEMRD#, and MEMWR# are used to read and write
to/from the control registers and the display memory. The two read
signals are connected directly with the RD# signal from the 386EX. The
two write signals are connected directly with the WR# signal from the
386EX.
The MPUCLK is connected to a 10 MHz clock generated in phase with
the PH1 clock in the FPGA. Since PH1 occurs at the beginning of each
386EX T state, the 1351 will be in synch with the 386EX.
RESET is connected directly with the RESET signal from the FPGA,
which goes to the 386EX.
The MPUSEL signal is tied to 3.3 volts via a resistor. This indicates that
the 1351 is to operate in word mode.
The BHE# signal is connected directly to the BHE# signal from the
386EX.
AB0-AB15 is connected to the address bus of the 386EX.
DB0-DB15 is connected to the bi-directional data bus BD0-BD15.
The above signals are all of the signals used to interface to the 386EX for
transferring of data to and from the control registers and the display RAM.