Mallinckrodt NELLCOR NPB-4000, Руководство по обслуживанию

Страница: 148 / 219

Section 14: Main Color Board Digital Theory of Operation
14-8
14.5.1 CPU SIGNALS
Various signals change at various times within a cycle, and the generic timing is
shown below. Some of the key signals are ADS#, M/IO#, D/C#, W/R#, WR#,
RD#, CS0-CS6#, BLE#, and BHE#. Typical control circuits will look at ADS#
at the end of PH2 and make decisions at this time. Refer to the 386EX timing
diagrams for a more detailed explanation.
Figure 14-3: CPU Timing Diagram
14.6 DRAM CONTROL
The DRAM control consists of one 1Mx16 EDO DRAM chip, three 74ACT157
address mux chips, address resistors, and the FPGA control circuit.
CS6* (* = # = / a low true signal) has been assigned to the DRAM memory
address space, 0-100000 words, or 0-200000 bytes. The CS6* control register in
the chip select unit (CSU) must be programmed for 1 WAIT STATE. Since the
data bus is 16 bits wide and the DRAM is a x16 part, most transfers will be of
the 16 bit variety. However, 8 bit transfers are allowed and we have made
provisions for byte addressing. This is done by using the upper and lower CAS
signals, UCAS and LCAS.
14.6.1 DRAM SIGNALS
For the DRAM design we must generate 6 signals, RAS#, UCAS#, LCAS#,
DRAMOE#, DRAMWR#, and CASADREN. All of these signals are generated
in the FPGA from the 386EX signals, ADS#, CS6#, M/IO#, D/C#, WR#, and
RD#. Since the CSU is programmed for 1 wait state, the CSU generates the
READY# signal which terminates the transfer.