Mallinckrodt NELLCOR NPB-4000, Руководство по обслуживанию

Страница: 174 / 219

Section 14: Main Color Board Digital Theory of Operation
14-34
14.17.18 READ BACK MULTIPLEXER
A read back multiplexer allows the software to read back programmed and status
signals from the FPGA. Register assignments are as follows:
1. PUMP/VALVE PWM 300 HEX
2. CONTRAST PWM 302 HEX, not used
3. SPEAKER HIGH VALUE 304 HEX
4. SPEAKER LOW VALUE 306 HEX
5. CONTROL REG 308 HEX
6. PUSH BUTTON STATUS 30A HEX
7. KNOB/MISC STATUS 30C HEX
8. MISC STATUS 30E HEX
14.17.19 NIBP PUMP/VALVE PWM CONTROL
This circuit consists of an 8 bit holding register and an 8 bit up/down counter.
This circuit is first used to control the NIBP pump by generating a pulse width
modulated signal which drives the pump on the POWER SUPPLY board. After
the pump has inflated the cuff, this same circuit is used to control opening the
valve to let the air out of the cuff. The pump PWM signal exits on pin 4 and the
valve PWM exits on pin 132. The enable for these 2 output buffers are
programmed in the control register and are mutually exclusive.
The software loads a value into the 8 bit holding register. The counter is clocked
by a 313 kHz clock and on all the time. When the counter overflows, the value
in the holding register is loaded into the counter synchronously with the 313 kHz
clock. The counter operates as a count up then count down circuit, always
generating the same frequency, but with different duty cycles. Once a value is
loaded into the counter, the counter counts up until it overflows. If
PUMP_PWM_GO is true, then the PUMP_PWM_FF is output on pin 3. When
the counter overflows, the PUMP_PWM_FF changes state, and the counter is
reloaded with the holding register’s value. Now the counter counts down until it
underflows, at which time, the flip flop changes state, the holding register’s
value is reloaded and counting continues in the up direction. Since the same
value is loaded each time, the total time for a count up and a count down is 313
kHz divided by 255, and, therefore, the signal frequency remains the same. The
duty cycle changes as the software programs the holding register, thus allowing
for a fully OFF to a fully ON signal with intermediate steps at a 3.2 us
resolution.