Mallinckrodt NELLCOR NPB-4000, Руководство по обслуживанию

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Section 11: Isolated Front End Functions -- Theory of Operation
11-9
11.8 CONTROLS
Figure 11-8: Controls Block Diagram
See Figure 11-8. The isolated control signals are developed and applied in the
highlighted blocks as shown in the block diagram.
Front end operations are controlled by serial signals on ADCTX line clocked by
signals on ADCCLK line. These serial signals from the Main Board CPU are
fed to the Front End through opto-isolators U55 and U56 with pull-ups R182 and
R173. Signals inverted by U61 go to eight-bit Serial-in/Parallel-out Shift
Register U66. The beginning of a stream sets up one-shot retriggerable
multivibrator U62A for the duration of 130 microseconds. The stream is 16 bits
long, and each pulse retriggers the one shot. At the end of the stream, and after a
130 microseconds time-out, the parallel set of bits representing the last eight bits
in the serial stream will be latched in an eight-bit buffer.
The bits represent different control functions. A group of three bits, MuxA,
MuxB, and MuxC, control eight-bit data multiplexer U67; and a group of two
bits, LSEL1 and LSEL2, control four-bit lead select multiplexers U79 and U78.
Two others are individual bits, 0.5 Hz controls corner frequency of the high-pass
filter, and ECGRES
controls baseline reset.
The bit assignment is as follows(MSB first):
Bit 9 Parity
Bit 10 ECGRES
Bit 11 0.5Hz
Bit 12 LSEL2
Bit 13 LSEL1
Bit 14 MuxC
Bit 15 MuxB
Bit 16
MuxA