DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Information Manual
Core Architecture
April 1998
5-2
DRAFT COPY
Lucent Technologies Inc.
(continued)
5.1.1 Inputs and Outputs
The XDB (instruction/coefficient data bus) provides coefficients to the x register and immediate data to the ALU.
The IDB (internal data bus) provides access to all of the other registers in the DAU. Flags are important DAU out-
puts to the control section.
5.1.2 Multiplier Functions
The multiplier executes a 16-bit
×
16-bit multiply and stores the 32-bit result in the product register (p) in one
instruction cycle. Data for the multiplier's inputs is stored in the 16-bit x register and the upper 16 bits (high half) of
the 32-bit y register. A single-cycle squaring function is achieved by setting the X=Y= bit in the auc register. In this
mode, any instruction that loads high half of the y register loads the x register with the same value. A subsequent
multiply then results in a squaring operation. (See
Section 4.5.5, Multiply/ALU Group
for more details.)
The x register can be directly loaded in one instruction cycle from X-memory space or Y-memory space with multi-
ply/ALU instructions.
The high half of the y register can be directly loaded from Y-memory space or the high or low half of an accumula-
tor in one instruction cycle. The y register also provides 32-bit data for the dyadic (two-operand) ALU functions
with an accumulator as the other input. For these, the y data is sign-extended to 36 bits.
Use of the 32-bit Y register:
y means high half, yl means low half, and y[l] means either.
If auc bit 6 = 0, yl is cleared with a write to y.
If auc bit 6 = 1, yl is not cleared with a write to y.
Writing yl does not affect y.
The 32-bit p register provides a 36-bit input for ALU functions by sign-extending bit 31. Unlike the a0, a1, or y reg-
isters, writing the high half of p does not change the data in the low half p regardless of the setting in the auc reg-
ister.
Registers x, y, yl, a0, a0l, a1, a1l, p, and pl are included in the general set of registers (see
) available for
use with the data move group of instructions.
5.1.3 ALU
In addition to being used as an adder in the multiply/accumulate instructions, the 36-bit ALU implements functions
and algorithms in the DSP1611/17/18/27/28/29 device that conventionally are executed in a microcomputer or a
microprocessor. Operands to the ALU can be data in y, p, a0, a1, or immediates. The ALU sign-extends 32-bit
operands from y or p to 36 bits and produces a 36-bit output (32 data bits and four guard bits) in one instruction
cycle. Either accumulator can receive the 36-bit result. The ALU supports dyadic (two-operand) functions (addi-
tion, subtraction, logical AND, OR, and XOR) between an accumulator and another accumulator, y, p, or an
immediate. The immediate is sign-extended up or zero-extended down depending on whether the low or high half
of the accumulator is specified. Monadic functions of an accumulator include rounding, negation, incrementation,
one's complement, and left and right shifts of 1, 4, 8, or 16 bits. The bit manipulation unit (BMU) (see
Chapter 13
,
) provides more complex accumulator functions.
The instruction groups using the ALU are as follows:
Special function instructions (F2); see
.
Multiply/ALU instructions; see
.
ALU instructions (F3); see
.
Содержание DSP1611
Страница 18: ...Chapter 1 Introduction...
Страница 27: ...Chapter 2 Hardware Architecture...
Страница 52: ...Chapter 3 Software Architecture...
Страница 116: ...Chapter 4 Instruction Set...
Страница 154: ...Chapter 5 Core Architecture...
Страница 176: ...Chapter 6 External Memory Interface...
Страница 208: ...Chapter 7 Serial I O...
Страница 237: ...Chapter 8 Parallel I O DSP1617 Only...
Страница 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Страница 275: ...Chapter 10 Bit I O Unit...
Страница 284: ...Chapter 11 JTAG Test Access Port...
Страница 306: ...Chapter 12 Timer...
Страница 313: ...Chapter 13 Bit Manipulation Unit...
Страница 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Страница 350: ...Chapter 15 Interface Guide...
Страница 367: ...Appendix A Instruction Encoding...
Страница 379: ...Appendix B Instruction Set Summary...
Страница 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Страница 437: ...Index...