LTC3882-1
56
Rev A
For more information
the lowest free running frequency created by the internal
VCO. This can be well below the intended PWM frequency
of the application and may cause undesirable operation of
the converter. For this reason, it is generally recommended
that a useable PWM frequency be programmed for each
channel, regardless of whether that particiular LTC3882-1
unit serves as clock master, or not.
All channels of a PolyPhase rail are required to share SYNC
pins. Between rails and for other configurations, such syn-
chronization is optional. If the SYNC pin is shared between
LTC3882-1s, only one LTC3882-1 should be programmed
to control the SYNC output.
PolyPhase Operation and Load Sharing
When the LTC3882-1 is used in a PolyPhase application,
the slave phases must be configured as such by con-
necting their FB pins to V
DD33
. Among other things, this
disables the error amplifiers of the slave phases. Five other
pins must then also be shared between all channels of a
PolyPhase rail:
• VINSNS
• COMP
• I
AVG
• I
AVG_GND
• SYNC
Using a common VINSNS connection reduces the dynamic
range required by the current loop and helps maintain
well-controlled master modulator gain.
The shared COMP signal allows the master phase error
amplifier to control the duty cycle of all slave phases to
produce the commanded output voltage.
Slave phases can detect system faults that cause the
master COMP (error amplifier) output to be too high. A
slave phase detecting this kind of error amplifier fault im-
mediately shuts off its PWM output, indicates the fault on
its VOUT_OV Fault bit, and takes whatever additional action
may be indicated by VOUT_OV_FAULT_RESPONSE for that
channel. If this response is set to only provide hardware-
level response (0x00), then normal channel operation will
automatically resume when the fault condition is cleared.
The shared I
AVG
and I
AVG_GND
signals actively balance the
amount of output current delivered from each channel using
a secondary current sharing loop. A capacitor with a value
between 100pF and 200pF should be placed between I
AVG
and I
AVG_GND
. This capacitance can be distributed across
LTC3882-1 devices/pins for improved noise immunity. All
I
AVG_GND
pins for a PolyPhase rail should be tied together
and connected to a single ground point at or near the
package paddle of the master phase.
Load sharing accuracy is based primarily on the current
sense amplifier offset of each phase (I
AVG_VOS
) and the
offset of slave current error amplifiers (V
SIOS
). These are
given in the EC table. Current sense gain errors between
LTC3882-1 channels will be negligible. The secondary
current sharing loop acts to average any errors among the
phases. Because of this error averaging and the random
nature of these variables, the EC table limits ensure actual
per-phase offset will be less than or equal to ±300µV for
most designs over the full operating temperature range.
This signifies better than ±2% matching when ∆I
SENSE
=
15mV, not including external factors such as DCR make
tolerance.
It is necessary to properly connect V
SENSE
+
on a slave
phase for accurate I
OUT
telemetry, even though slave phases
do use need this information for PWM control. While not
strictly required, the V
SENSE
±
lines of slave phases can
simply share with the master to provide additional output
voltage telemetry. If the only concern is accurate slave I
OUT
telemetry, V
SENSE
+
for that channel may be locally wired
to I
SENSE
–
. V
SENSE
–
on a slave phase should always be
shorted to V
SENSE
–
for its master channel. I
OUT
OC/ROC
function is not affected by V
SENSE
±
wiring.
All phases must be synchronized to the same shared
SYNC clock and should be programmed to run at the
same default PWM frequency. Phases should be selected
to be evenly spaced around a 360° phasor diagram, and
all phases on a PolyPhase rail should be selected to have
the same maximum duty cycle. Refer to details for MFR_
PWM_CONFIG_LTC3882-1. Figure 38 shows an example
of connections for three phases and Figure 39 shows an
example of an 8-phase rail. Additional shared signals in
these figures highlight the ability of the LTC3882-1 to com-
municate fault status between phases and rails, perform
APPLICATIONS INFORMATION
