LTC3882-1
26
Rev A
For more information
OPERATION
Refer to the Absolute Maximum Ratings for other important
temperature limitations on internal EEPROM use.
External temperature sensors may also be monitored by
the onboard ADC. There is no hardwired PWM response
for sensed external temperature faults or warnings.
Hardwired PWM Response to Timing Faults
There is no hardwired PWM response to any timing faults.
TON_MAX_FAULT_LIMIT is the time allowed for V
OUT
to
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
timer, which has a resolution of 10µs, is started after
TON_DELAY has been reached and a soft-start sequence
is started. If the VOUT_UV_FAULT_LIMIT is not reached or
an OC remains within the specified time, fault response is
determined by the value of TON_MAX_FAULT_RESPONSE.
An internal watchdog detects if SHARE_CLK remains
low for more than 64µs. The part then actively holds
SHARE_CLK low for 120ms, ensuring all devices connected
to this shared control observe a minimum RETRY_DELAY
event.The LTC3882-1 sets the SHARE_CLK_LOW bit in
MFR_COMMON to indicate this fault condition.
External Faults
There are no hardware-level responses to any external
faults propagated into the IC through the
FAULT
n
pins.
Fault Handling
Higher-level input and output fault event handling (response)
can be programmed as described in the following PMBus
Command Details section. For most faults, the LTC3882-1
can manage response in one of three ways: ignore, autono-
mous recovery (hiccup), or latch off. The device takes no
additional action beyond previously discussed hardware-
level responses when programmed to ignore a fault.
For autonomous recovery a new soft-start is attempted if
the fault condition is not present after the MFR_RETRY_
DELAY interval has elapsed. MFR_RETRY_DELAY can be
set from 120ms to 83 seconds in 1ms increments. If the
fault persists, the controller will continue to retry with an
interval specified by the MFR_RETRY_DELAY command.
This avoids damage to external regulator components
caused by repetitive, rapid power cycling.
No retry is attempted for a latch off fault response. In the
latch off state the gate drivers for the external MOSFETs
are immediately disabled to stop the transfer of energy
to the load as quickly as possible. The output remains
disabled until the channel is commanded off and then
on, or IC supply power is cycled. Commanding a PWM
channel off and on may require software and/or hardware
intervention depending on its programmed configuration.
The RUN pin must be released by any controlling external
application circuits for that channel to restart from the latch
off state. As the RUN pin for a given channel rises, associ-
ated internal fault indications are cleared automatically. The
LTC3882-1 can also be programmed to clear faults for both
outputs based solely on the RUN voltage of just one chan-
nel. See the MFR_CONFIG_ALL_LTC3882-1 command. The
CLEAR_FAULTS PMBus command can also be used to clear
all fault bits at any time, independent of PWM channel state.
Handling of some internally generated faults can be digitally
deglitched. See Table 12. External faults propagated into
the chip using
FAULT
n
pins are not deglitched. Refer to
the following section on
FAULT
functions.
Status Registers and
ALERT
Masking
Figure 2 summarizes the internal LTC3882-1 status reg-
isters accessible by PMBus command. These contain
indication of various faults, warnings and other important
operating conditions. As shown, the STATUS_BYTE and
STATUS_WORD commands also summarize contents of
other status registers. Refer to PMBus Command Details
for specific information.
NONE OF THE ABOVE in STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
In general, any asserted bit in a STATUS_x register also
pulls the
ALERT
pin low. Once set,
ALERT
will remain low
until one of the following occurs.
• A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_RE-
SET Command Is Issued
• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and
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