LTC3882-1
18
Rev A
For more information
OPERATION
VINSNS
38821 F01
LTC3882-1
I
AVG0
V
SENSE0
+
38
I
SENSE0
+
5
I
AVG_GND
40
FB0
1
COMP0
(RANGE 0)
35
V
SENSE0
–
37
I
SENSE0
–
PWM0
9R
LOOP
COMPENSATION
NETWORK
2R
R
S
V
IN
V
OC0
C
S
L1
C
OUT
V
OUT
–
+
MODE
36
IOUT_OC_FAULT_LIMIT
V
REV
EA
VC
+
–
CA
+
–
S
GATE
DRIVER
PWM
LOGIC
OSCILLATOR
RAMP
CLOCK
Q
0V
R
S
MASTER
ENABLE
SLAVE
ENABLE
39
SLAVE
DETECT
FEED
FORWARD
I
LIM
I
REV
4
+
V
SP0
VOUT_COMMAND
12-BIT DAC
8-BIT DAC
V
OV0
OV
UV
VOUT_OV_FAULT_LIMIT
9-BIT DAC
V
UV0
VOUT_UV_FAULT_LIMIT
9-BIT DAC
7
Figure 1. LTC3882-1 PWM Control Loop Diagram