Lexicon RV-8, Руководство по обслуживанию

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Lexicon
Signals received from the user terminal enter the system via J4 pin B3. This signal is ferrite bead de-
coupled to remove spurious high frequency noise, which drives U5 pin 8 as the signal RXDB. The output
of this driver provides the receive signal to the Host CPU as USER_RXD from U5 pin 9.
W1 and W2 are test points for ease of debug.
C12-C13 provides a high frequency path to ground for noise entering the system from the outside world.
DSR and RLSD signals from the terminals are not used, and so they are pulled up to +5VD via R21-R24.
J4 is a dual stacked DB9-F connector; DB9 is the standard profile for RS-232.
Analog Board Connector (J26)
J26 is a 40 position Flat Flex Cable (FFC) connector. All digital audio streams and their associated clocks
are either sourced from the FPGA to the Analog Board, or they return to the FPGA from the Analog
Board. Detailed description of these signals may be found on page 6-37. Signals not previously discussed
or bearing special consideration are as follows:
RESET is an active high signal generated by Reset Generator U31. It provides power-up reset to the
Analog Board and is the only positive going reset signal in use in the RV-8 system.
Amp Board Connectors (J18 and J22)
J18 is a 14 position FFC connector that provides interconnection with the Crown Four Channel Amplifier
Module. A ferrite bead de-coupled 5V is supplied to the module to power the SPI control logic. The ferrite
is necessary for the suppression of parasitic frequencies that would compromise the RFI integrity of the
amplifiers. The SPI port signals SER_CLKA, CTRL_DATA, STAT_DATA, and DATA_LATCHA are
discussed in greater depth on page 6-38 and will not be expanded upon here.
Each channel amplifier contains a thermistor that monitors heat sink temperatures local to each channel’s
output transistors. This information is provided to the A/D inputs of the Host CPU in the form of a voltage
that increases proportionally with temperature. TEMP[4:1] are the voltages for the four channel module.
See page 6-12 for more information.
J22 is the same form factor as J18, and performs the same function. The only difference is that this
component provides interconnectivity with the Crown Three Channel Amplifier Module. TEMP[7:5]
provides temperature monitoring to the Host CPU in the same manner as on the four channel module.
AMP_RESET/ is a buffered equivalent active low reset signal as provided by Reset Generator U31. This
is used to clear the SPI logic on the modules to zero.
SPARE_AD is intended as a monitoring signal for the amplifier power supply. To date, this has not been
implemented in the design.
Front Panel Connector (J20)
J20 is a 40 position FFC connector that conveys all the signals necessary to control and report status of
the front panel LED array, the pushbutton array, the rotary encoder, and the Vacuum-Fluorescent
Display.
FP_RESET/ is a buffered equivalent of the active low reset signal generated by U31. This signal is used
to reset the state machines controlling the LED matrix, and the switch status.
SYSTEM_ON_LED is a buffered equivalent of the SYSLED signal, which is driven directly by the Host
CPU. The SYSTEM ON LED is one of three LEDs located behind the VFD lens on the front panel.
6-41