Lexicon RV-8, Руководство по обслуживанию

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RV-8 Service Manual
FB15 provides a cleaner 3.3V supply to the oscillator, minimizing contamination of the output clock signal
by the switching characteristics of other devices connected to the 3.3VD plane. C142 is a standard high
frequency de-coupling capacitor for U35.
Expansion Slot Connectors (J25, J30)
J25 and J30 are connectors that will provide system inter-connectivity for accessory boards that will
enhance product capabilities. An eighteen bit wide bus from the FPGA is source impedance split into two
different paths to the connectors. These signals are currently bi-directional in nature and have no clearly
defined function as of yet.
J25 and J30 are 34-position Flat Flex Cable Connectors (FFC) that provide a 5VD supply to the
expansion card via four pins. The contact impedance of the connector pins to FFC cable is such that
future expansion cards should not draw more than one amp of current from the 5VD supply. Ground and
signal return path is provided via ten pins on each connector. J25-3 is an active low reset signal
EXPA_RESET/ , while J30-3 has a separate active low reset signal EXPB_RESET/ . Both resets are Host
Processor controlled and allows each expansion slot to be reset independently.
Expansion Port Series Terminations (Sheet 11)
This page further illustrates the source impedance splitting of the expansion bus mentioned in the
preceding section. RP29-RP37 provide source impedance matching for each of the eighteen bus signals
originating from the AVRX FPGA. Each signal connects to two resistors, the opposite ends of which
connect to J25 and J30. The effect is that the bus is shared between both connectors, but each slot has
it’s own impedance path back to the FPGA pins.
Board Interconn/Debug (Sheet 12)
This page contains all of the off-board interconnections to the Front Panel Board, Video Board, Analog IO
Board, and Amplifier Modules. This page also contains the Debug and User Access RS-232 terminal
ports.
RS-232 Transceiver (U5)
U5 is a Maxim MAX202E dual RS-232 Transceiver that runs on 5V
B DC B
whereas most transceivers need +/-
12 V
B
DC
B
to accommodate the +/-10V swing intrinsic to RS-232. This device uses charge pump voltage
conversion to accomplish this. C28 doubles the 5V present in the circuit to 10V, storing it on C27. The
second charge pump inverts the +10V to –10V, storing it on C30. Using this technology, the output drive
capability on pins 9 and 12 is +/-8V when loaded with a nominal 5K-Ohm RS-232 receiver. This conforms
to the EIA/TIA-232E and V28 specifications for RS-232.
The debug transmit signal DEBUG_TXD from the CPU drives pin 11 of U5. This driver is output as TXDA
on pin 14, and is ferrite bead de-coupled to remove spurious high frequency noise before being output on
J4.
Signals received from the debug terminal enter the system via J4 pin A3. This signal is ferrite bead de-
coupled to remove spurious high frequency noise, which drives U5 pin 13 as the signal RXDA. The output
of this driver provides the receive signal to the Host CPU as DEBUG_RXD from U5 pin 12.
The user transmit signal USER_TXD from the CPU drives pin 10 of U5. This driver is output as TXDB on
pin 7, and is ferrite bead de-coupled to remove spurious high frequency noise before being output on J4.
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