Lexicon RV-8, Руководство по обслуживанию

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RV-8 Service Manual
OVLD_LED is a buffered equivalent of the OVLED signal, which is driven directly by the Host CPU. The
OVERLOAD LED is one of three LEDs located behind the VFD lens on the front panel. U15 provides the
buffered signals from the CPU to the Front Panel Board.
FP_IR_BLINK is a repeater signal from the ZONE 2 remote control detector plugged into the back of the
RV8. This signal causes an infrared LED to blink which in turn is sensed by the front panel IR detector.
FP_IR_BLINK_RET is the return current path from the front panel infra-red LED.
FP_IR_IN1 is the output signal from the infra-red detector on the front panel. Whenever a signal from a
hand held remote control is detected, the IR detector outputs a Hamming Code signal to the AVRX FPGA
which then decodes the command. The Host CPU then reads and processes the code accordingly.
FP_IR_ACK is a signal driven directly from the Host CPU to a front panel LED indicator. This LED flashes
whenever a hand-held remote control access has been made. It serves as a visual verification that the
remote signal is being received.
FP_ENC(A,B)_IN are rotary encoder output signals. R172-R175, C165, and C170 are low-pass filtering
and pull-up networks for these quadrature signals. See page 6-30 for further information regarding these
signals.
FP_SDATA_IN is the signal by which the AVRX FPGA receives data back from the CPLD on the Front
Panel Board with regards to the status of the pushbutton array
FP_SDATA_OUT is the signal by which the AVRX FPGA transmits data to the CPLD on the Front Panel
Board in order to write to the LED array.
SDATA_CLK is the clock signal that controls the serial shift of data up and back from the FPGA front
panel.
FP_SDATA_LTCH is a signal that marks the beginning of an eight bit sample being transmitted to the
front panel.
All four of these signals comprise the SPI interface to the front panel.
DISP_RS is an address decoded bank select for the VFD.
DISP_RW is an address decoded read/write strobe for the VFD. When this signal is high, the VFD
registers are in read mode. When low, the registers are in write mode.
DISP_E is an address decoded global enable of the VFD.
FP_D[7:0] is an eight-bit data bus to the VFD. All register accesses to the VFD are made via this bus.
FPSWITCH[3:1 ] are breakout signals from the RIGHT MODE, MAIN DVD2, and ZONE 2 DVD2 buttons
on the front panel. The Host CPU monitors these signals. The boot-up state of these switches determines
the operational mode RV8 will enter once boot-up is complete. See page 6-8 for further details.
Supply vo3.3VD and +5VD are both needed to power the Front Panel Board. The IR/ENCODER
Board, VFD, and LED matrix are powered by +5VD, while the CPLD is powered by +3.3VD.
6-42