6800/6.3
6800/6.3
330/6.3
330/6.3
33/10
33/10
1A
+5VD
4.7/6.3
4.7/6.3
.1/25
.1/25
10
442
1%
1.00K
1%
1.00K
1%
AGND
AVDD
GND1
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND2
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND3
GND4
GND5
GND6
GND7
GND8
GND9
NC1
NC2
NC3
NC4
NC5
VDDEXT1
VDDEXT10
VDDEXT11
VDDEXT12
VDDEXT13
VDDEXT2
VDDEXT3
VDDEXT4
VDDEXT5
VDDEXT6
VDDEXT7
VDDEXT8
VDDEXT9
VDDINT1
VDDINT10
VDDINT11
VDDINT12
VDDINT13
VDDINT14
VDDINT2
VDDINT3
VDDINT4
VDDINT5
VDDINT6
VDDINT7
VDDINT8
VDDINT9
ADSP-21161N
POWER BLOCK
.01/25
+3.3VD
+5VD
DESCRIPTION
REV
CHECKER
DRAFTER
AUTH.
Q.C.
REVISIONS
1
SIZE
OF
3
2
A
B
C
D
1
2
3
4
5
6
7
8
4
5
6
7
8
A
B
C
D
NUMBER
CODE
Q.C.
ISSUED
DATE
APPROVALS
CONTRACT
NO.
SHEET
FILE NAME
B
DRAWN
CHECKED
TITLE
exicon
REV
3 OAK PARK
BEDFORD, MA 01730
+3.3VD
+5VD
.01/25
ADJ
TERM
VIN
VOUT
LM1117
ADJ
TERM
VIN
VOUT
LM1117
AGND
AVDD
GND1
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND2
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND3
GND4
GND5
GND6
GND7
GND8
GND9
NC1
NC2
NC3
NC4
NC5
VDDEXT1
VDDEXT10
VDDEXT11
VDDEXT12
VDDEXT13
VDDEXT2
VDDEXT3
VDDEXT4
VDDEXT5
VDDEXT6
VDDEXT7
VDDEXT8
VDDEXT9
VDDINT1
VDDINT10
VDDINT11
VDDINT12
VDDINT13
VDDINT14
VDDINT2
VDDINT3
VDDINT4
VDDINT5
VDDINT6
VDDINT7
VDDINT8
VDDINT9
ADSP-21161N
POWER BLOCK
CK
GND
VCC
OE
GAL16V8R-15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
+1.8V-A
+1.8V-B
442
1%
10
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
DIR
GND
VCC
G
74VHCT245
+5VD
1A
5/2/04
KAB
4/29/04
CW
CAM
4/29/04
4/27/04
RWH
ECM
10/9/03
MAG
10/9/03
CAM
10/2/03
CHANGED PER DCR 030626-00
RWH
9/29/03
MAG
5/20/03
5/20/03
CW
5/2/03
RWH
CAM
5/14/03
2
CHANGED PER DCR 030307-00
MAG
12/20/02
12/20/02
CW
11/06/02
CAM
11/05/02
RWH
1
CHANGED PER DCR 020913-00
RWH
CAM
CW
JV
4/30/02
5/1/02
4/30/02
4/26/02
060-15559
1.8V
1.8V
.
SCHEM, MAIN BD,RV8
DSP/FPGA POWER CONN.
3
4
4
ECO 040422-00
CHANGED C73, 75, 130, 133 PER
7
19
15559-6
5-
6-
2004_9:
30
7
DSPBAVDD
+1.8V-A
[1/B3]
CPUCS3/
D47
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
19
1
18
20
10
U43
R76
R78
DISP_E
[12/B6]
DISP_RW
[12/B6]
DISP_RS
[12/B6]
CLK12500B
[3/D4]
FP_D[7:0]
[12/B6]
FP_D3
FP_D4
FP_D2
FP_D5
FP_D1
FP_D6
FP_D0
FP_D7
CPUDATA[15:0]
[1/D3,2/D7]
CPUDATA0
CPUDATA1
CPUDATA2
CPUDATA3
CPUDATA4
CPUDATA5
CPUDATA6
CPUDATA7
CPUWRL/
[1/B3,9/C8]
[2/C7]
RESREGDECL
CPUCLKI
[1/C8]
[1/B3]
CPUWRH/
CPURD/
[1/B3,9/C8]
CPUADDR3
CPUADDR2
CPUADDR1
CPUADDR[20:0]
[1/D3,9/C7]
20
10
11
1
19
18
17
16
15
14
13
12
3
9
7
6
5
4
2
8
+
52010542
U44
P14
N14
C3
G9
G10
H6
H7
H8
H9
J6
J7
J8
F6
J9
J10
K6
K7
K8
K9
K10
F7
F8
F9
G7
G8
A1
A15
B15
R1
R15
E5
E11
G11
J11
L11
G5
J5
L5
E7
L7
E9
M8
D8
K5
K11
L6
L8
L10
E6
E8
E10
F5
F11
H3
H5
H11
L9
H10
F10
G6
U16
NC
NC
NC
NC
2
3
4
1
U39
2
3
4
1
U22
DSPAAVDD
C128
C71
NC
NC
NC
NC
NC
NC
P14
N14
C3
G9
G10
H6
H7
H8
H9
J6
J7
J8
F6
J9
J10
K6
K7
K8
K9
K10
F7
F8
F9
G7
G8
A1
A15
B15
R1
R15
E5
E11
G11
J11
L11
G5
J5
L5
E7
L7
E9
M8
D8
K5
K11
L6
L8
L10
E6
E8
E10
F5
F11
H3
H5
H11
L9
H10
F10
G6
U34
RESREGDECH
[2/A7]
R143
R77
R144
R142
C72
C129
C67
C127
D37
[9/D2]
DISP_CTRL
1.8V-B
C74
C131
C133
C75
C73
C130
Содержание RV-8
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