+3.3VD
ADSP-21161N
D0A
D0B
D1A
D1B
D2A
D2B
D3A
D3B
FS1
FS2
FS3
L0ACK
L0CLK
L0DAT00
L0DAT01
L0DAT02
L0DAT03
L0DAT04
L0DAT05
L0DAT06
L0DAT07
L1ACK
L1CLK
L1DAT00
L1DAT01
L1DAT02
L1DAT03
L1DAT04
L1DAT05
L1DAT06
L1DAT07
MISO
MOSI
SCLK0
SCLK1
SCLK2
SCLK3
SPICLK
SPIDS
FS0
SPI BLOCK
DESCRIPTION
REV
CHECKER
DRAFTER
AUTH.
Q.C.
REVISIONS
1
SIZE
OF
3
2
A
B
C
D
1
2
3
4
5
6
7
8
4
5
6
7
8
A
B
C
D
NUMBER
CODE
Q.C.
ISSUED
DATE
APPROVALS
CONTRACT
NO.
SHEET
FILE NAME
B
DRAWN
CHECKED
TITLE
exicon
REV
3 OAK PARK
BEDFORD, MA 01730
ADSP-21161N
D0A
D0B
D1A
D1B
D2A
D2B
D3A
D3B
FS1
FS2
FS3
L0ACK
L0CLK
L0DAT00
L0DAT01
L0DAT02
L0DAT03
L0DAT04
L0DAT05
L0DAT06
L0DAT07
L1ACK
L1CLK
L1DAT00
L1DAT01
L1DAT02
L1DAT03
L1DAT04
L1DAT05
L1DAT06
L1DAT07
MISO
MOSI
SCLK0
SCLK1
SCLK2
SCLK3
SPICLK
SPIDS
FS0
SPI BLOCK
+3.3VD
ECM
10/9/03
MAG
10/9/03
CAM
10/2/03
CHANGED PER DCR 030626-00
RWH
9/29/03
MAG
5/20/03
5/20/03
CW
5/2/03
RWH
CAM
5/14/03
2
CHANGED PER DCR 030307-00
MAG
12/20/02
12/20/02
CW
11/06/02
CAM
11/05/02
RWH
1
CHANGED PER DCR 020913-00
RWH
CAM
CW
JV
4/30/02
5/1/02
4/30/02
4/26/02
SCHEM, MAIN BD,RV8
060-15559
.
DSP SPI, SERIAL AND LINK PORTS
3
3
6
19
15559-6
5-
6-
2004_9:
30
6
R74
10K
DSPBSP3FPGA
[9/B8]
DSPASP0FPGA
[9/C8]
R140
10K
[8/C8,9/C2]
DSPATXD
[8/C8,9/C2]
DSPARXD
[8/C8,9/C2]
DSPASPICLK
SPORT_CLK_B
[9/B8]
DSPB2DSPA
DSPA2DSPB
DSPABLDATA7
DSPABLDATA6
DSPABLDATA5
DSPABLDATA4
DSPABLDATA3
DSPABLDATA2
DSPABLDATA1
DSPABLDATA0
DSPABLDATA0
DSPABLDATA1
DSPABLDATA2
DSPABLDATA3
DSPABLDATA4
DSPABLDATA5
DSPABLDATA6
DSPABLDATA7
DSPABLDATA[7:0]
DSPBALDATA[7:0]
DSPBALDATA0
DSPBALDATA1
DSPBALDATA2
DSPBALDATA3
DSPBALDATA4
DSPBALDATA5
DSPBALDATA6
DSPBALDATA7
DSPBALDATA7
DSPBALDATA0
DSPBALDATA1
DSPBALDATA2
DSPBALDATA3
DSPBALDATA4
DSPBALDATA5
DSPBALDATA6
DSPBSEL/
[9/C2]
E4
C5
C6
D6
C7
B7
B8
A8
D7
C8
C9
A10
B10
E12
B11
A11
D11
A9
D10
C10
B9
B13
A13
B14
C13
A14
C12
B12
D12
A12
C11
D4
B4
D5
B6
A7
D9
C4
A4
B5
U16
NC
NC
NC
NC
NC
DSPASEL/
[9/C2]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E4
C5
C6
D6
C7
B7
B8
A8
D7
C8
C9
A10
B10
E12
B11
A11
D11
A9
D10
C10
B9
B13
A13
B14
C13
A14
C12
B12
D12
A12
C11
D4
B4
D5
B6
A7
D9
C4
A4
B5
U34
SPORT_CLK_A
[9/C8]
SPORT_FS_B_N
[9/B8]
R73
10K
SPORT_FS_A_N
[9/C8]
[9/C8]
DSPASP3FPGA
Содержание RV-8
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