Lexicon RV-8, Руководство по обслуживанию

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Lexicon
Address Bits Signal
Base + 0 3:0 Ready control for channels 4:1 (RDY_CON[4:1])
Base + 0 7:4 (Not used)
Base + 1 7:0 (Not used)
Four Channel Control RAM Table
SER_CLKA is the serial shift clock with which the control and status data are synchronous.
DATA_LATCHA is the signal that latches control and status data into registers when a full byte of data
has been transmitted or received.
STAT_DATB is the receive path from the three-channel power amplifier. Data from this signal is stored in
a 2x8 bit RAM internal to the AVRX, from which the host may determine the ready status and clip status
of each channel. The following table illustrates the mapping of the internal RAM.
Address Bits Signal
Base + 0 7:0 Control bits [7:0] from the previous SPI cycle
Base + 1 2:0 Ready monitor for channels 7:5 (RDY_MON[7:5])
Base + 1 3 (Not used)
Base + 1 6:4 Clip indicator for channels 7:5 (CLIP7:5)
Base + 1 7 (Not used)
Three Channel Status RAM Table
CTRL_DATB is the transmit path to the three-channel power amplifier. Control data from the Host CPU is
loaded into an internal 2x8 bit RAM that is in turn serially shifted out to the three-channel amplifier board.
The only control data currently being transmitted is in the form of three ready acknowledge bits, each of
which activates a relay that places the speaker terminals into circuit with the amplifier outputs. The
following table illustrates the mapping of the internal RAM.
Address Bits Signal
Base + 0 2:0 Ready control for channels 7:5 (RDY_CON[7:5])
Base + 0 7:3 (Not used)
Base + 1 7:0 (Not used)
Three Channel Control RAM Table
SER_CLKB is the serial shift clock with which the control and status data are synchronous.
DATA_LATCHB is the signal that latches control and status data into registers when a full byte of data
has been transmitted or received.
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