Lexicon RV-8, Руководство по обслуживанию

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RV-8 Service Manual
rQQ: Value Read
The actual value (in hexadecimal) that was read from the address where the failure occurred.
POWER ON DIAGNOSTICS
As described earlier there are two power-on modes in the RV-8. You can power on via the rear panel
power switch or by bringing the RV-8 out of standby mode. Power-on diagnostics are executed every time
the rear panel power switch is switched on. Diagnostics are not run when the unit is brought out of
standby.
The power-on diagnostics take approximately fifty seconds to complete. The power-on diagnostics are
intended to verify basic hardware functionality of an RV-8. Additional diagnostic tests are available to
completely test the hardware, and for debugging failures.
Initially, an attempt is made to illuminate the VFD and front panel LEDs for approximately five seconds.
However, during the first four tests the VFD will not be considered functional due to it not being tested.
During these tests, Trap Op Code, SH Flash Checksum, SH DRAM, and VFD RAM, the unit will attempt
to use the standby LED to indicate if a failure occurs. As soon as these tests are completed the VFD will
display:
“DIAGNOSTIC TESTS
… …”
The dots increment in number from both sides simultaneously, as the rest of the power-on diagnostic
tests are completed. This informs you that the unit is still functioning. The audio outputs (digital and
analog) will be muted during this sequence.
The following is a list of test explanations. The front panel display is shown only for the first test that can
use the VFD. The reference designators used are from Revision 5 Main Board 710-15550 used on BOM
023-15615. The schematics for the main board are 060-15559.
Trap Opcode
The Trap Opcode error occurs if during the initial boot sequence an undefined Opcode is fetched. The
INT/TRAP Control register can be used to determine the starting address of the undefined instruction. If
the trap error occurs, an attempt will be made to blink the standby LED using a rate of a single blink per
several seconds, and the test will attempt to enter a loop to exercise signal lines to aid in debugging.
SH Flash Checksum Test
The SH Flash Checksum test verifies U26 on the Main Board, has the correct program by adding up all
the values in memory and checking it against the value stored. The checksum is reported to the Serial
Debug Port. The test verifies that the calculated checksum matches the checksum value stored in the
flash. If an error occurs an attempt will be made to blink the standby LED using a rate of a two blinks per
several seconds, and the test will attempt to enter a loop to exercise signal lines to aid in debugging.
SH DRAM Test
The SH DRAM test performs write and read testing on the DRAM. The test uses patterns 0x00, 0xFFFF,
0x5555, and 0xAAAA. Once each location in the DRAM is verified, a walking 1s check is done to test
address buss integrity. If an error occurs, an attempt will be made to blink the STANDBY LED using a rate
of three blinks per several seconds, and the test will attempt to enter a loop to exercise signal lines to aid
in debugging.
5-6