Lexicon RV-8, Руководство по обслуживанию

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Lexicon
DISP_RS is a decode of CPUCS3/ and the condition CPUADDR[3:1] == 001. This is an active low signal
and is a function bank select signal for the VFD.
DISP_RW is a read/write strobe for the VFD. When this signal is high, the VFD registers are in read
mode. When low, the registers are in write mode. This signal is a decode of CPURD/ , CPUCS3/ , and the
condition CPUADDR[3:1] == 001 or == 010.
DISP_E is a global enable of the VFD and is a decode of CPUCS3/ and CPUADDR[3:1] == 001 or ==
010. This is an active high signal.
VFD Data Bus Transceiver (U43)
This device is a byte wide, bi-directional tristate buffer interface for the VFD data bus. The buffer’s
direction and tristate controls are address decoded signals from CPLD U44. When write cycles are
performed to the VFD Display Control Register (CPU Address 0x00C00003) or the VFD Data Register
(CPU Address 0x00C00005), the tri-state buffer is enabled, and data flow is from the CPU to the VFD.
When read cycles are performed at these register locations, The buffer is enabled and data flow is from
the VFD to the CPU. When these register locations are not addressed for access, the tristate buffer is
disabled and the IO pins float.
Format DSP (Sheet 8)
This sheet contains the format DSP, associated FLASH RAM algorithm memory, timing circuitry, and
delay components necessary for proper interfacing between the DSP and RAM.
Format DSP (U25)
This device decodes all the “canned” algorithm information from the input data streams provided by the
FPGA. This device is a Crystal Semiconductor CS494001 Multi-Standard Audio Decoder. It is packaged
in a 144 pin LQFP. In truth, this decoder is actually two DSP engines in one package (DSPAB and
DSPC). Each engine has it’s own SPI port for host communication.
Power Up State
Signals: CRY_RESET/, FHS[2:0], UHS[2:0]
When the RV8 is first powered up, the Format DSP is placed in a reset state by the signal CRY_RESET/
going low. This signal is controlled by external register U21, which will hold U25 in reset until released by
the system software. When this reset is asserted high, pins
FHS[2:0] and UHS[2:0] are sampled on the
rising edge of CRY_RESET/ . FHS[2:0] sets the host interface mode for DSPAB to SPI serial mode by
hardwiring these pins to a binary value of 101. UHS[2:0] performs the same function for DSPC, and is
hardwired to a binary value of 101, again selecting SPI serial mode.
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