LeCroy 4300B, Руководство оператора

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The I
RU
currents, which determine the ADC gains, are controlled by the
VRU supply, adjustable via the VRU potentiometer. The VRU potential is
adjusted to obtain an average of 0.5 pC/count for 8 and 9 bits of resolu-
tion to 0.25 pC/count for 10 and 11 bits of resolution. The pedestal
compensation I
PC
currents are controlled by a voltage adjustable by
means of the P potentiometer. This voltage is adjusted so that the
average pedestal variation is zero with a GATE varying between 50 nsec
and 500 nsec. This adjustment depends on the VRU voltage. The
amplitude of the pedestal injection charges is adjustable by means of the
O potentiometer. It is adjusted to obtain an average pedestal of 8 pC.
This adjustment does not affect any other adjustment and if necessary
may be readjusted for GATE width greater than 500 nsec.
2.4 Test Circuit The test charge is injected at the input of the MQTs by the discharge of a
200 pf C
t
capacitor, via a resistor fan-out (see Figure 2.2). An amplifier,
controlled by the voltage applied on the TRV input, charges C
t
to a
voltage equal to that of the TRV while compensating the voltage differ-
ence between the VGND and the module ground. The test charge may
be adjusted via the T potentiometer. It is adjusted to obtain an average
charge on each ADC of 50 pC/V.
The test is controlled by a monostable triggered by the CAMAC function
F(25) A(0).S2. The monostable output width is 550 nsec. It opens the
GATE, and after a delay of 20 nsec, turns on the MOSFET switch, which
discharges the C
t
capacitor into all 16 analog inputs through the 16
resistor fan out.
2.5 Digital Interpolators In order to accelerate the time to digital conversion, digital interpolators
are used between the time output of the MQT200Fs and the real time
counters. The following description refers to Figure 2.3. Each interpolator
is made of four latches controlled by four clock signals at 4 nsec inter-
vals. Looking at the different consecutive states of these four clock
signals, it can be seen that the time function of the four signals follows a
gray code rule, i.e., only one of the four signals changes its state at a
time.
Each digital interpolator memorizes the state of the gray code when it
receives a high to low transition from the time output. During readout, the
four gray code bits are converted into binary code to form the three least
significant bits of the data word. The real time counter clock is generated
by the fourth interpolator latch output. The high to low transition of this
output indicates the transition from state 7 to 0, and results in the
incrementation of the real time counter.
2.6 Real Time Counters The 16 real time counters are packaged in four hybrid, LeCroy type
ls408, circuits. Each circuit contains four independent, 8 bit scalers, each
with latches and tri-state out buffers. The following description refers to
Figure 2.3
. At the end of a GATE signal, the real time counters are
cleared by the 400 nsec monostable and the latches are activated for the
entire digitization duration by the FS monostable. After the digitization,
these latches memorize the state of the real time counters. During the
interpolator readout a transition may appear on the clock of the real time
counters. The real time counters are incremented by each high to low
interpolator output transition, that is, in module 8. The three bits of the
interpolator associated with the eight bits of the real time counter form
the eleven bits of the ADC data word.